# AVR JTAG Pinout

When designing an application PCB, which includes an Atmel AVR with the JTAG interface, it is recommended to use the pinout as shown in the figure below. Both 100-mil and 50-mil variants of this pinout are supported, depending on the cabling and adapters included with the particular kit.

Figure 1. AVR JTAG Header Pinout

Table 1. AVR JTAG Pin Description
Name | Pin | Description
--- | --- | ---
TCK | 1 | Test Clock (clock signal from the Atmel-ICE into the target device).
TMS | 5 | Test Mode Select (control signal from the Atmel-ICE into the target device).
TDI | 9 | Test Data In (data transmitted from the Atmel-ICE into the target device).
TDO | 3 | Test Data Out (data transmitted from the target device into the Atmel-ICE).
nTRST | 8 | Test Reset (optional, only on some AVR devices). Used to reset the JTAG TAP controller.
nSRST | 6 | Reset (optional). Used to reset the target device. Connecting this pin is recommended since it allows the Atmel-ICE to hold the target device in a reset state, which can be essential to debugging in certain scenarios.
VTG | 4 | Target voltage reference. The Atmel-ICE samples the target voltage on this pin in order to power the level converters correctly. The Atmel-ICE draws less than 3mA from this pin in debugWIRE mode and less than 1mA in other modes.
GND | 2, 10 | Ground. Both must be connected to ensure that the Atmel-ICE and the target device share the same ground reference.

Tip: Remember to include a decoupling capacitor between pin 4 and GND.
Parent topic: JTAG Physical Interface