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  1. cpldfit: version P.20131013 Xilinx Inc.
  2. Fitter Report
  3. Design Name: counta Date: 8- 4-2020, 0:40AM
  4. Device Used: XC9572XL-5-VQ44
  5. Fitting Status: Successful
  6. ************************* Mapped Resource Summary **************************
  7. Macrocells Product Terms Function Block Registers Pins
  8. Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
  9. 42 /72 ( 58%) 227 /360 ( 63%) 86 /216 ( 40%) 42 /72 ( 58%) 11 /34 ( 32%)
  10. ** Function Block Resources **
  11. Function Mcells FB Inps Pterms IO
  12. Block Used/Tot Used/Tot Used/Tot Used/Tot
  13. FB1 7/18 25/54 47/90 7/ 9
  14. FB2 11/18 22/54 57/90 0/ 9
  15. FB3 18/18* 22/54 84/90 2/ 9
  16. FB4 6/18 17/54 39/90 2/ 7
  17. ----- ----- ----- -----
  18. 42/72 86/216 227/360 11/34
  19. * - Resource is exhausted
  20. ** Global Control Resources **
  21. Global clock net(s) unused.
  22. Global output enable net(s) unused.
  23. Global set/reset net(s) unused.
  24. ** Pin Resources **
  25. Signal Type Required Mapped | Pin Type Used Total
  26. ------------------------------------|------------------------------------
  27. Input : 2 2 | I/O : 8 28
  28. Output : 9 9 | GCK/IO : 3 3
  29. Bidirectional : 0 0 | GTS/IO : 0 2
  30. GCK : 0 0 | GSR/IO : 0 1
  31. GTS : 0 0 |
  32. GSR : 0 0 |
  33. ---- ----
  34. Total 11 11
  35. ** Power Data **
  36. There are 42 macrocells in high performance mode (MCHP).
  37. There are 0 macrocells in low power mode (MCLP).
  38. End of Mapped Resource Summary
  39. ************************** Errors and Warnings ***************************
  40. WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
  41. use the default filename of 'counta.ise'.
  42. ************************* Summary of Mapped Logic ************************
  43. ** 9 Outputs **
  44. Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
  45. Name Pts Inps No. Type Use Mode Rate State
  46. LED<0> 7 10 FB1_6 41 I/O O STD FAST RESET
  47. LED<1> 7 10 FB1_8 42 I/O O STD FAST RESET
  48. LED<2> 7 10 FB1_9 43 GCK/I/O O STD FAST RESET
  49. LED<3> 7 10 FB1_11 44 GCK/I/O O STD FAST RESET
  50. LED<4> 7 10 FB1_14 1 GCK/I/O O STD FAST RESET
  51. LED<5> 7 10 FB1_15 2 I/O O STD FAST RESET
  52. LED<6> 5 12 FB1_17 3 I/O O STD FAST RESET
  53. LED<7> 4 12 FB3_2 5 I/O O STD FAST RESET
  54. TX 6 9 FB3_5 6 I/O O STD FAST RESET
  55. ** 33 Buried Nodes **
  56. Signal Total Total Loc Pwr Reg Init
  57. Name Pts Inps Mode State
  58. clkcounta<9> 5 14 FB2_8 STD RESET
  59. clkcounta<8> 5 13 FB2_9 STD RESET
  60. clkcounta<7> 5 12 FB2_10 STD RESET
  61. clkcounta<6> 5 11 FB2_11 STD RESET
  62. clkcounta<5> 5 10 FB2_12 STD RESET
  63. clkcounta<4> 5 9 FB2_13 STD RESET
  64. clkcounta<3> 5 8 FB2_14 STD RESET
  65. clkcounta<12> 5 17 FB2_15 STD RESET
  66. clkcounta<11> 5 16 FB2_16 STD RESET
  67. clkcounta<10> 5 15 FB2_17 STD RESET
  68. storecounta<13> 7 10 FB2_18 STD RESET
  69. alreadystoredcnt<0> 3 7 FB3_1 STD RESET
  70. uartskip<0> 3 7 FB3_3 STD RESET
  71. clkcounta<0> 3 5 FB3_4 STD RESET
  72. uartctr<4> 4 12 FB3_6 STD RESET
  73. uartctr<3> 4 12 FB3_7 STD RESET
  74. uartctr<2> 4 12 FB3_8 STD RESET
  75. uartctr<1> 4 12 FB3_9 STD RESET
  76. uartctr<0> 4 12 FB3_10 STD RESET
  77. clkcounta<2> 5 7 FB3_11 STD RESET
  78. clkcounta<1> 5 6 FB3_12 STD RESET
  79. storecounta<2> 6 9 FB3_13 STD RESET
  80. storecounta<1> 6 9 FB3_14 STD RESET
  81. resetclk<0> 2 3 FB3_15 STD RESET
  82. storecounta<5> 7 10 FB3_16 STD RESET
  83. storecounta<4> 7 10 FB3_17 STD RESET
  84. storecounta<3> 7 10 FB3_18 STD RESET
  85. storecounta<14> 7 10 FB4_1 STD RESET
  86. storecounta<18> 6 8 FB4_13 STD RESET
  87. storecounta<17> 6 9 FB4_14 STD RESET
  88. storecounta<16> 6 9 FB4_15 STD RESET
  89. storecounta<6> 7 10 FB4_17 STD RESET
  90. storecounta<15> 7 10 FB4_18 STD RESET
  91. ** 2 Inputs **
  92. Signal Loc Pin Pin Pin
  93. Name No. Type Use
  94. XSTALIN FB4_5 20 I/O I
  95. HZIN FB4_8 21 I/O I
  96. Legend:
  97. Pin No. - ~ - User Assigned
  98. ************************** Function Block Details ************************
  99. Legend:
  100. Total Pt - Total product terms used by the macrocell signal
  101. Imp Pt - Product terms imported from other macrocells
  102. Exp Pt - Product terms exported to other macrocells
  103. in direction shown
  104. Unused Pt - Unused local product terms remaining in macrocell
  105. Loc - Location where logic was mapped in device
  106. Pin Type/Use - I - Input GCK - Global Clock
  107. O - Output GTS - Global Output Enable
  108. (b) - Buried macrocell GSR - Global Set/Reset
  109. X - Signal used as input to the macrocell logic.
  110. Pin No. - ~ - User Assigned
  111. *********************************** FB1 ***********************************
  112. Number of function block inputs used/remaining: 25/29
  113. Number of signals used by logic mapping into function block: 25
  114. Signal Total Imp Exp Unused Loc Pin Pin Pin
  115. Name Pt Pt Pt Pt # Type Use
  116. (unused) 0 0 0 5 FB1_1 (b)
  117. (unused) 0 0 0 5 FB1_2 39 I/O
  118. (unused) 0 0 0 5 FB1_3 (b)
  119. (unused) 0 0 0 5 FB1_4 (b)
  120. (unused) 0 0 \/1 4 FB1_5 40 I/O (b)
  121. LED<0> 7 2<- 0 0 FB1_6 41 I/O O
  122. (unused) 0 0 /\1 4 FB1_7 (b) (b)
  123. LED<1> 7 2<- 0 0 FB1_8 42 I/O O
  124. LED<2> 7 4<- /\2 0 FB1_9 43 GCK/I/O O
  125. (unused) 0 0 /\4 1 FB1_10 (b) (b)
  126. LED<3> 7 2<- 0 0 FB1_11 44 GCK/I/O O
  127. (unused) 0 0 /\2 3 FB1_12 (b) (b)
  128. (unused) 0 0 \/2 3 FB1_13 (b) (b)
  129. LED<4> 7 2<- 0 0 FB1_14 1 GCK/I/O O
  130. LED<5> 7 2<- 0 0 FB1_15 2 I/O O
  131. (unused) 0 0 /\2 3 FB1_16 (b) (b)
  132. LED<6> 5 0 0 0 FB1_17 3 I/O O
  133. (unused) 0 0 0 5 FB1_18 (b)
  134. Signals Used by Logic in Function Block
  135. 1: HZIN 10: XSTALIN 18: resetclk<0>
  136. 2: LED<0> 11: alreadystoredcnt<0> 19: storecounta<13>
  137. 3: LED<1> 12: clkcounta<4> 20: uartctr<0>
  138. 4: LED<2> 13: clkcounta<5> 21: uartctr<1>
  139. 5: LED<3> 14: clkcounta<6> 22: uartctr<2>
  140. 6: LED<4> 15: clkcounta<7> 23: uartctr<3>
  141. 7: LED<5> 16: clkcounta<8> 24: uartctr<4>
  142. 8: LED<6> 17: clkcounta<9> 25: uartskip<0>
  143. 9: LED<7>
  144. Signal 1 2 3 4 FB
  145. Name 0----+----0----+----0----+----0----+----0 Inputs
  146. LED<0> XXX....XXXXX.....X......X............... 10
  147. LED<1> X.XX...XXXX.X....X......X............... 10
  148. LED<2> X..XX..XXXX..X...X......X............... 10
  149. LED<3> X...XX.XXXX...X..X......X............... 10
  150. LED<4> X....XXXXXX....X.X......X............... 10
  151. LED<5> X.....XXXXX.....XXX.....X............... 10
  152. LED<6> X......XXXX......X.XXXXXX............... 12
  153. 0----+----1----+----2----+----3----+----4
  154. 0 0 0 0
  155. *********************************** FB2 ***********************************
  156. Number of function block inputs used/remaining: 22/32
  157. Number of signals used by logic mapping into function block: 22
  158. Signal Total Imp Exp Unused Loc Pin Pin Pin
  159. Name Pt Pt Pt Pt # Type Use
  160. (unused) 0 0 /\2 3 FB2_1 (b) (b)
  161. (unused) 0 0 0 5 FB2_2 29 I/O
  162. (unused) 0 0 0 5 FB2_3 (b)
  163. (unused) 0 0 0 5 FB2_4 (b)
  164. (unused) 0 0 0 5 FB2_5 30 I/O
  165. (unused) 0 0 0 5 FB2_6 31 I/O
  166. (unused) 0 0 0 5 FB2_7 (b)
  167. clkcounta<9> 5 0 0 0 FB2_8 32 I/O (b)
  168. clkcounta<8> 5 0 0 0 FB2_9 33 GSR/I/O (b)
  169. clkcounta<7> 5 0 0 0 FB2_10 (b) (b)
  170. clkcounta<6> 5 0 0 0 FB2_11 34 GTS/I/O (b)
  171. clkcounta<5> 5 0 0 0 FB2_12 (b) (b)
  172. clkcounta<4> 5 0 0 0 FB2_13 (b) (b)
  173. clkcounta<3> 5 0 0 0 FB2_14 36 GTS/I/O (b)
  174. clkcounta<12> 5 0 0 0 FB2_15 37 I/O (b)
  175. clkcounta<11> 5 0 0 0 FB2_16 (b) (b)
  176. clkcounta<10> 5 0 0 0 FB2_17 38 I/O (b)
  177. storecounta<13> 7 2<- 0 0 FB2_18 (b) (b)
  178. Signals Used by Logic in Function Block
  179. 1: HZIN 9: clkcounta<12> 16: clkcounta<7>
  180. 2: LED<6> 10: clkcounta<1> 17: clkcounta<8>
  181. 3: LED<7> 11: clkcounta<2> 18: clkcounta<9>
  182. 4: XSTALIN 12: clkcounta<3> 19: resetclk<0>
  183. 5: alreadystoredcnt<0> 13: clkcounta<4> 20: storecounta<13>
  184. 6: clkcounta<0> 14: clkcounta<5> 21: storecounta<14>
  185. 7: clkcounta<10> 15: clkcounta<6> 22: uartskip<0>
  186. 8: clkcounta<11>
  187. Signal 1 2 3 4 FB
  188. Name 0----+----0----+----0----+----0----+----0 Inputs
  189. clkcounta<9> X..XXX...XXXXXXXXXX..................... 14
  190. clkcounta<8> X..XXX...XXXXXXXX.X..................... 13
  191. clkcounta<7> X..XXX...XXXXXXX..X..................... 12
  192. clkcounta<6> X..XXX...XXXXXX...X..................... 11
  193. clkcounta<5> X..XXX...XXXXX....X..................... 10
  194. clkcounta<4> X..XXX...XXXX.....X..................... 9
  195. clkcounta<3> X..XXX...XXX......X..................... 8
  196. clkcounta<12> X..XXXXXXXXXXXXXXXX..................... 17
  197. clkcounta<11> X..XXXXX.XXXXXXXXXX..................... 16
  198. clkcounta<10> X..XXXX..XXXXXXXXXX..................... 15
  199. storecounta<13> XXXXX.X...........XXXX.................. 10
  200. 0----+----1----+----2----+----3----+----4
  201. 0 0 0 0
  202. *********************************** FB3 ***********************************
  203. Number of function block inputs used/remaining: 22/32
  204. Number of signals used by logic mapping into function block: 22
  205. Signal Total Imp Exp Unused Loc Pin Pin Pin
  206. Name Pt Pt Pt Pt # Type Use
  207. alreadystoredcnt<0> 3 1<- /\3 0 FB3_1 (b) (b)
  208. LED<7> 4 0 /\1 0 FB3_2 5 I/O O
  209. uartskip<0> 3 0 0 2 FB3_3 (b) (b)
  210. clkcounta<0> 3 0 \/1 1 FB3_4 (b) (b)
  211. TX 6 1<- 0 0 FB3_5 6 I/O O
  212. uartctr<4> 4 0 0 1 FB3_6 (b) (b)
  213. uartctr<3> 4 0 0 1 FB3_7 (b) (b)
  214. uartctr<2> 4 0 0 1 FB3_8 7 I/O (b)
  215. uartctr<1> 4 0 \/1 0 FB3_9 8 I/O (b)
  216. uartctr<0> 4 1<- \/2 0 FB3_10 (b) (b)
  217. clkcounta<2> 5 2<- \/2 0 FB3_11 12 I/O (b)
  218. clkcounta<1> 5 2<- \/2 0 FB3_12 (b) (b)
  219. storecounta<2> 6 2<- \/1 0 FB3_13 (b) (b)
  220. storecounta<1> 6 1<- 0 0 FB3_14 13 I/O (b)
  221. resetclk<0> 2 0 \/3 0 FB3_15 14 I/O (b)
  222. storecounta<5> 7 3<- \/1 0 FB3_16 18 I/O (b)
  223. storecounta<4> 7 2<- 0 0 FB3_17 16 I/O (b)
  224. storecounta<3> 7 3<- /\1 0 FB3_18 (b) (b)
  225. Signals Used by Logic in Function Block
  226. 1: HZIN 9: clkcounta<2> 16: storecounta<6>
  227. 2: LED<6> 10: resetclk<0> 17: uartctr<0>
  228. 3: LED<7> 11: storecounta<1> 18: uartctr<1>
  229. 4: TX 12: storecounta<2> 19: uartctr<2>
  230. 5: XSTALIN 13: storecounta<3> 20: uartctr<3>
  231. 6: alreadystoredcnt<0> 14: storecounta<4> 21: uartctr<4>
  232. 7: clkcounta<0> 15: storecounta<5> 22: uartskip<0>
  233. 8: clkcounta<1>
  234. Signal 1 2 3 4 FB
  235. Name 0----+----0----+----0----+----0----+----0 Inputs
  236. alreadystoredcnt<0> XXX.XX...X...........X.................. 7
  237. LED<7> XXX.XX...X......XXXXXX.................. 12
  238. uartskip<0> XXX.XX...X...........X.................. 7
  239. clkcounta<0> X...XXX..X.............................. 5
  240. TX XXXXXX...XX..........X.................. 9
  241. uartctr<4> XXX.XX...X......XXXXXX.................. 12
  242. uartctr<3> XXX.XX...X......XXXXXX.................. 12
  243. uartctr<2> XXX.XX...X......XXXXXX.................. 12
  244. uartctr<1> XXX.XX...X......XXXXXX.................. 12
  245. uartctr<0> XXX.XX...X......XXXXXX.................. 12
  246. clkcounta<2> X...XXXXXX.............................. 7
  247. clkcounta<1> X...XXXX.X.............................. 6
  248. storecounta<2> XXX.XX...X.XX........X.................. 9
  249. storecounta<1> XXX.XX...XXX.........X.................. 9
  250. resetclk<0> X...XX.................................. 3
  251. storecounta<5> XXX.XX..XX....XX.....X.................. 10
  252. storecounta<4> XXX.XX.X.X...XX......X.................. 10
  253. storecounta<3> XXX.XXX..X..XX.......X.................. 10
  254. 0----+----1----+----2----+----3----+----4
  255. 0 0 0 0
  256. *********************************** FB4 ***********************************
  257. Number of function block inputs used/remaining: 17/37
  258. Number of signals used by logic mapping into function block: 17
  259. Signal Total Imp Exp Unused Loc Pin Pin Pin
  260. Name Pt Pt Pt Pt # Type Use
  261. storecounta<14> 7 4<- /\2 0 FB4_1 (b) (b)
  262. (unused) 0 0 /\4 1 FB4_2 19 I/O (b)
  263. (unused) 0 0 0 5 FB4_3 (b)
  264. (unused) 0 0 0 5 FB4_4 (b)
  265. (unused) 0 0 0 5 FB4_5 20 I/O I
  266. (unused) 0 0 0 5 FB4_6 (b)
  267. (unused) 0 0 0 5 FB4_7 (b)
  268. (unused) 0 0 0 5 FB4_8 21 I/O I
  269. (unused) 0 0 0 5 FB4_9 (b)
  270. (unused) 0 0 0 5 FB4_10 (b)
  271. (unused) 0 0 0 5 FB4_11 22 I/O
  272. (unused) 0 0 \/3 2 FB4_12 (b) (b)
  273. storecounta<18> 6 3<- \/2 0 FB4_13 (b) (b)
  274. storecounta<17> 6 2<- \/1 0 FB4_14 23 I/O (b)
  275. storecounta<16> 6 1<- 0 0 FB4_15 27 I/O (b)
  276. (unused) 0 0 \/2 3 FB4_16 (b) (b)
  277. storecounta<6> 7 2<- 0 0 FB4_17 28 I/O (b)
  278. storecounta<15> 7 2<- 0 0 FB4_18 (b) (b)
  279. Signals Used by Logic in Function Block
  280. 1: HZIN 7: clkcounta<11> 13: storecounta<16>
  281. 2: LED<0> 8: clkcounta<12> 14: storecounta<17>
  282. 3: LED<6> 9: clkcounta<3> 15: storecounta<18>
  283. 4: LED<7> 10: resetclk<0> 16: storecounta<6>
  284. 5: XSTALIN 11: storecounta<14> 17: uartskip<0>
  285. 6: alreadystoredcnt<0> 12: storecounta<15>
  286. Signal 1 2 3 4 FB
  287. Name 0----+----0----+----0----+----0----+----0 Inputs
  288. storecounta<14> X.XXXXX..XXX....X....................... 10
  289. storecounta<18> X.XXXX...X....X.X....................... 8
  290. storecounta<17> X.XXXX...X...XX.X....................... 9
  291. storecounta<16> X.XXXX...X..XX..X....................... 9
  292. storecounta<6> XXXXXX..XX.....XX....................... 10
  293. storecounta<15> X.XXXX.X.X.XX...X....................... 10
  294. 0----+----1----+----2----+----3----+----4
  295. 0 0 0 0
  296. ******************************* Equations ********************************
  297. ********** Mapped Logic **********
  298. FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),XSTALIN,'0','0');
  299. LED_D(0) <= ((NOT LED(6) AND LED(0) AND NOT HZIN)
  300. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  301. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  302. OR (LED(6) AND LED(1) AND alreadystoredcnt(0))
  303. OR (LED(6) AND LED(1) AND NOT HZIN)
  304. OR (NOT LED(6) AND LED(0) AND alreadystoredcnt(0))
  305. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(4)));
  306. FDCPE_LED1: FDCPE port map (LED(1),LED_D(1),XSTALIN,'0','0');
  307. LED_D(1) <= ((NOT LED(6) AND LED(1) AND NOT HZIN)
  308. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  309. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  310. OR (LED(6) AND LED(2) AND alreadystoredcnt(0))
  311. OR (LED(6) AND LED(2) AND NOT HZIN)
  312. OR (NOT LED(6) AND LED(1) AND alreadystoredcnt(0))
  313. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(5)));
  314. FDCPE_LED2: FDCPE port map (LED(2),LED_D(2),XSTALIN,'0','0');
  315. LED_D(2) <= ((NOT LED(6) AND LED(2) AND alreadystoredcnt(0))
  316. OR (NOT LED(6) AND LED(2) AND NOT HZIN)
  317. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(6))
  318. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  319. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  320. OR (LED(6) AND LED(3) AND alreadystoredcnt(0))
  321. OR (LED(6) AND LED(3) AND NOT HZIN));
  322. FDCPE_LED3: FDCPE port map (LED(3),LED_D(3),XSTALIN,'0','0');
  323. LED_D(3) <= ((NOT LED(6) AND LED(3) AND NOT HZIN)
  324. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  325. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  326. OR (LED(6) AND LED(4) AND alreadystoredcnt(0))
  327. OR (LED(6) AND LED(4) AND NOT HZIN)
  328. OR (NOT LED(6) AND LED(3) AND alreadystoredcnt(0))
  329. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(7)));
  330. FDCPE_LED4: FDCPE port map (LED(4),LED_D(4),XSTALIN,'0','0');
  331. LED_D(4) <= ((NOT LED(6) AND LED(4) AND NOT HZIN)
  332. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  333. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  334. OR (LED(6) AND LED(5) AND alreadystoredcnt(0))
  335. OR (LED(6) AND LED(5) AND NOT HZIN)
  336. OR (NOT LED(6) AND LED(4) AND alreadystoredcnt(0))
  337. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(8)));
  338. FDCPE_LED5: FDCPE port map (LED(5),LED_D(5),XSTALIN,'0','0');
  339. LED_D(5) <= ((NOT LED(6) AND LED(5) AND NOT HZIN)
  340. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  341. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  342. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(13))
  343. OR (LED(6) AND storecounta(13) AND NOT HZIN)
  344. OR (NOT LED(6) AND LED(5) AND alreadystoredcnt(0))
  345. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(9)));
  346. FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),XSTALIN,'0','0');
  347. LED_T(6) <= ((NOT LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  348. NOT resetclk(0) AND NOT uartskip(0))
  349. OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  350. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  351. uartctr(3) AND uartctr(4))
  352. OR (LED(6) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
  353. uartskip(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  354. uartctr(3) AND uartctr(4))
  355. OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
  356. uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
  357. uartctr(4) AND NOT HZIN));
  358. FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),XSTALIN,'0','0');
  359. LED_T(7) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  360. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  361. OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  362. NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
  363. uartctr(2) AND uartctr(3) AND uartctr(4))
  364. OR (NOT LED(7) AND LED(6) AND NOT alreadystoredcnt(0) AND
  365. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  366. uartctr(3) AND uartctr(4) AND NOT HZIN));
  367. FDCPE_TX: FDCPE port map (TX,TX_D,XSTALIN,'0','0');
  368. TX_D <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  369. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  370. OR (LED(6) AND NOT resetclk(0) AND storecounta(1))
  371. OR (NOT LED(6) AND NOT resetclk(0) AND TX)
  372. OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(1) AND
  373. HZIN)
  374. OR (NOT LED(6) AND NOT alreadystoredcnt(0) AND HZIN AND TX));
  375. FDCPE_alreadystoredcnt0: FDCPE port map (alreadystoredcnt(0),alreadystoredcnt_D(0),XSTALIN,'0','0');
  376. alreadystoredcnt_D(0) <= ((LED(7) AND NOT LED(6) AND NOT resetclk(0) AND uartskip(0) AND
  377. NOT HZIN)
  378. OR (NOT alreadystoredcnt(0) AND NOT HZIN));
  379. FDCPE_clkcounta0: FDCPE port map (clkcounta(0),clkcounta_D(0),XSTALIN,'0','0');
  380. clkcounta_D(0) <= ((NOT resetclk(0) AND NOT clkcounta(0))
  381. OR (NOT alreadystoredcnt(0) AND HZIN AND NOT clkcounta(0)));
  382. FDCPE_clkcounta1: FDCPE port map (clkcounta(1),clkcounta_D(1),XSTALIN,'0','0');
  383. clkcounta_D(1) <= ((NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  384. NOT clkcounta(1))
  385. OR (NOT alreadystoredcnt(0) AND HZIN AND NOT clkcounta(0) AND
  386. clkcounta(1))
  387. OR (NOT resetclk(0) AND clkcounta(0) AND NOT clkcounta(1))
  388. OR (NOT resetclk(0) AND NOT clkcounta(0) AND clkcounta(1)));
  389. FTCPE_clkcounta2: FTCPE port map (clkcounta(2),clkcounta_T(2),XSTALIN,'0','0');
  390. clkcounta_T(2) <= ((NOT resetclk(0) AND clkcounta(0) AND clkcounta(1))
  391. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  392. clkcounta(1))
  393. OR (alreadystoredcnt(0) AND resetclk(0) AND clkcounta(2))
  394. OR (resetclk(0) AND NOT HZIN AND clkcounta(2)));
  395. FTCPE_clkcounta3: FTCPE port map (clkcounta(3),clkcounta_T(3),XSTALIN,'0','0');
  396. clkcounta_T(3) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(3))
  397. OR (resetclk(0) AND NOT HZIN AND clkcounta(3))
  398. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  399. clkcounta(2))
  400. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  401. clkcounta(1) AND clkcounta(2)));
  402. FTCPE_clkcounta4: FTCPE port map (clkcounta(4),clkcounta_T(4),XSTALIN,'0','0');
  403. clkcounta_T(4) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(4))
  404. OR (resetclk(0) AND NOT HZIN AND clkcounta(4))
  405. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  406. clkcounta(2) AND clkcounta(3))
  407. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  408. clkcounta(1) AND clkcounta(2) AND clkcounta(3)));
  409. FTCPE_clkcounta5: FTCPE port map (clkcounta(5),clkcounta_T(5),XSTALIN,'0','0');
  410. clkcounta_T(5) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(5))
  411. OR (resetclk(0) AND NOT HZIN AND clkcounta(5))
  412. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  413. clkcounta(2) AND clkcounta(3) AND clkcounta(4))
  414. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  415. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4)));
  416. FTCPE_clkcounta6: FTCPE port map (clkcounta(6),clkcounta_T(6),XSTALIN,'0','0');
  417. clkcounta_T(6) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(6))
  418. OR (resetclk(0) AND NOT HZIN AND clkcounta(6))
  419. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  420. clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5))
  421. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  422. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
  423. clkcounta(5)));
  424. FTCPE_clkcounta7: FTCPE port map (clkcounta(7),clkcounta_T(7),XSTALIN,'0','0');
  425. clkcounta_T(7) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(7))
  426. OR (resetclk(0) AND NOT HZIN AND clkcounta(7))
  427. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  428. clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
  429. clkcounta(6))
  430. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  431. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
  432. clkcounta(5) AND clkcounta(6)));
  433. FTCPE_clkcounta8: FTCPE port map (clkcounta(8),clkcounta_T(8),XSTALIN,'0','0');
  434. clkcounta_T(8) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(8))
  435. OR (resetclk(0) AND NOT HZIN AND clkcounta(8))
  436. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  437. clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
  438. clkcounta(6) AND clkcounta(7))
  439. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  440. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
  441. clkcounta(5) AND clkcounta(6) AND clkcounta(7)));
  442. FTCPE_clkcounta9: FTCPE port map (clkcounta(9),clkcounta_T(9),XSTALIN,'0','0');
  443. clkcounta_T(9) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(9))
  444. OR (resetclk(0) AND NOT HZIN AND clkcounta(9))
  445. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  446. clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
  447. clkcounta(6) AND clkcounta(7) AND clkcounta(8))
  448. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  449. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
  450. clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8)));
  451. FTCPE_clkcounta10: FTCPE port map (clkcounta(10),clkcounta_T(10),XSTALIN,'0','0');
  452. clkcounta_T(10) <= ((alreadystoredcnt(0) AND resetclk(0) AND
  453. clkcounta(10))
  454. OR (resetclk(0) AND NOT HZIN AND clkcounta(10))
  455. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
  456. clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
  457. clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9))
  458. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  459. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
  460. clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
  461. clkcounta(9)));
  462. FTCPE_clkcounta11: FTCPE port map (clkcounta(11),clkcounta_T(11),XSTALIN,'0','0');
  463. clkcounta_T(11) <= ((alreadystoredcnt(0) AND resetclk(0) AND
  464. clkcounta(11))
  465. OR (resetclk(0) AND NOT HZIN AND clkcounta(11))
  466. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(10) AND
  467. clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
  468. clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
  469. clkcounta(9))
  470. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  471. clkcounta(10) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
  472. clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
  473. clkcounta(8) AND clkcounta(9)));
  474. FTCPE_clkcounta12: FTCPE port map (clkcounta(12),clkcounta_T(12),XSTALIN,'0','0');
  475. clkcounta_T(12) <= ((alreadystoredcnt(0) AND resetclk(0) AND
  476. clkcounta(12))
  477. OR (resetclk(0) AND NOT HZIN AND clkcounta(12))
  478. OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(10) AND
  479. clkcounta(11) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
  480. clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
  481. clkcounta(8) AND clkcounta(9))
  482. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
  483. clkcounta(10) AND clkcounta(11) AND clkcounta(1) AND clkcounta(2) AND
  484. clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
  485. clkcounta(7) AND clkcounta(8) AND clkcounta(9)));
  486. FDCPE_resetclk0: FDCPE port map (resetclk(0),resetclk_D(0),XSTALIN,'0','0');
  487. resetclk_D(0) <= (NOT alreadystoredcnt(0) AND HZIN);
  488. FDCPE_storecounta1: FDCPE port map (storecounta(1),storecounta_D(1),XSTALIN,'0','0');
  489. storecounta_D(1) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  490. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  491. OR (LED(6) AND NOT resetclk(0) AND storecounta(2))
  492. OR (NOT LED(6) AND NOT resetclk(0) AND storecounta(1))
  493. OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(2) AND
  494. HZIN)
  495. OR (NOT LED(6) AND NOT alreadystoredcnt(0) AND storecounta(1) AND
  496. HZIN));
  497. FDCPE_storecounta2: FDCPE port map (storecounta(2),storecounta_D(2),XSTALIN,'0','0');
  498. storecounta_D(2) <= ((NOT LED(6) AND storecounta(2))
  499. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  500. uartskip(0) AND NOT HZIN)
  501. OR (LED(6) AND storecounta(3))
  502. OR (alreadystoredcnt(0) AND resetclk(0))
  503. OR (resetclk(0) AND NOT HZIN));
  504. FDCPE_storecounta3: FDCPE port map (storecounta(3),storecounta_D(3),XSTALIN,'0','0');
  505. storecounta_D(3) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(3))
  506. OR (NOT LED(6) AND storecounta(3) AND NOT HZIN)
  507. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  508. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  509. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(4))
  510. OR (LED(6) AND storecounta(4) AND NOT HZIN)
  511. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0)));
  512. FDCPE_storecounta4: FDCPE port map (storecounta(4),storecounta_D(4),XSTALIN,'0','0');
  513. storecounta_D(4) <= ((NOT LED(6) AND storecounta(4) AND NOT HZIN)
  514. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  515. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  516. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(5))
  517. OR (LED(6) AND storecounta(5) AND NOT HZIN)
  518. OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(4))
  519. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(1)));
  520. FDCPE_storecounta5: FDCPE port map (storecounta(5),storecounta_D(5),XSTALIN,'0','0');
  521. storecounta_D(5) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(5))
  522. OR (NOT LED(6) AND storecounta(5) AND NOT HZIN)
  523. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  524. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  525. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(6))
  526. OR (LED(6) AND storecounta(6) AND NOT HZIN)
  527. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(2)));
  528. FDCPE_storecounta6: FDCPE port map (storecounta(6),storecounta_D(6),XSTALIN,'0','0');
  529. storecounta_D(6) <= ((NOT LED(6) AND storecounta(6) AND NOT HZIN)
  530. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  531. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  532. OR (LED(6) AND LED(0) AND alreadystoredcnt(0))
  533. OR (LED(6) AND LED(0) AND NOT HZIN)
  534. OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(6))
  535. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(3)));
  536. FDCPE_storecounta13: FDCPE port map (storecounta(13),storecounta_D(13),XSTALIN,'0','0');
  537. storecounta_D(13) <= ((NOT LED(6) AND storecounta(13) AND NOT HZIN)
  538. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  539. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  540. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(14))
  541. OR (LED(6) AND storecounta(14) AND NOT HZIN)
  542. OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(13))
  543. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(10)));
  544. FDCPE_storecounta14: FDCPE port map (storecounta(14),storecounta_D(14),XSTALIN,'0','0');
  545. storecounta_D(14) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(14))
  546. OR (NOT LED(6) AND storecounta(14) AND NOT HZIN)
  547. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(11))
  548. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  549. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  550. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(15))
  551. OR (LED(6) AND storecounta(15) AND NOT HZIN));
  552. FDCPE_storecounta15: FDCPE port map (storecounta(15),storecounta_D(15),XSTALIN,'0','0');
  553. storecounta_D(15) <= ((NOT LED(6) AND storecounta(15) AND NOT HZIN)
  554. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  555. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  556. OR (LED(6) AND alreadystoredcnt(0) AND storecounta(16))
  557. OR (LED(6) AND storecounta(16) AND NOT HZIN)
  558. OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(15))
  559. OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(12)));
  560. FDCPE_storecounta16: FDCPE port map (storecounta(16),storecounta_D(16),XSTALIN,'0','0');
  561. storecounta_D(16) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  562. uartskip(0) AND NOT HZIN)
  563. OR (LED(6) AND storecounta(17))
  564. OR (NOT LED(6) AND storecounta(16))
  565. OR (alreadystoredcnt(0) AND resetclk(0))
  566. OR (resetclk(0) AND NOT HZIN));
  567. FDCPE_storecounta17: FDCPE port map (storecounta(17),storecounta_D(17),XSTALIN,'0','0');
  568. storecounta_D(17) <= ((NOT LED(6) AND NOT alreadystoredcnt(0) AND storecounta(17) AND
  569. HZIN)
  570. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  571. NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
  572. OR (LED(6) AND NOT resetclk(0) AND storecounta(18))
  573. OR (NOT LED(6) AND NOT resetclk(0) AND storecounta(17))
  574. OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(18) AND
  575. HZIN));
  576. FDCPE_storecounta18: FDCPE port map (storecounta(18),storecounta_D(18),XSTALIN,'0','0');
  577. storecounta_D(18) <= ((LED(6) AND NOT alreadystoredcnt(0) AND HZIN)
  578. OR (NOT alreadystoredcnt(0) AND storecounta(18) AND HZIN)
  579. OR (LED(7) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
  580. uartskip(0) AND NOT HZIN)
  581. OR (LED(6) AND NOT resetclk(0))
  582. OR (NOT resetclk(0) AND storecounta(18)));
  583. FTCPE_uartctr0: FTCPE port map (uartctr(0),uartctr_T(0),XSTALIN,'0','0');
  584. uartctr_T(0) <= ((LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  585. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  586. uartctr(3) AND uartctr(4))
  587. OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  588. NOT resetclk(0) AND uartskip(0))
  589. OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
  590. uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
  591. uartctr(4) AND NOT HZIN));
  592. FTCPE_uartctr1: FTCPE port map (uartctr(1),uartctr_T(1),XSTALIN,'0','0');
  593. uartctr_T(1) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  594. NOT resetclk(0) AND uartskip(0) AND uartctr(0))
  595. OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  596. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  597. uartctr(3) AND uartctr(4))
  598. OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
  599. uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
  600. uartctr(4) AND NOT HZIN));
  601. FTCPE_uartctr2: FTCPE port map (uartctr(2),uartctr_T(2),XSTALIN,'0','0');
  602. uartctr_T(2) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  603. NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1))
  604. OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  605. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  606. uartctr(3) AND uartctr(4))
  607. OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
  608. uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
  609. uartctr(4) AND NOT HZIN));
  610. FTCPE_uartctr3: FTCPE port map (uartctr(3),uartctr_T(3),XSTALIN,'0','0');
  611. uartctr_T(3) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  612. NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
  613. uartctr(2))
  614. OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  615. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  616. uartctr(3) AND uartctr(4))
  617. OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
  618. uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
  619. uartctr(4) AND NOT HZIN));
  620. FTCPE_uartctr4: FTCPE port map (uartctr(4),uartctr_T(4),XSTALIN,'0','0');
  621. uartctr_T(4) <= ((LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  622. NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
  623. uartctr(3) AND uartctr(4))
  624. OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
  625. NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
  626. uartctr(2) AND uartctr(3))
  627. OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
  628. uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
  629. uartctr(4) AND NOT HZIN));
  630. FTCPE_uartskip0: FTCPE port map (uartskip(0),uartskip_T(0),XSTALIN,'0','0');
  631. uartskip_T(0) <= ((NOT LED(7) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
  632. NOT uartskip(0))
  633. OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
  634. NOT resetclk(0) AND uartskip(0) AND NOT HZIN));
  635. Register Legend:
  636. FDCPE (Q,D,C,CLR,PRE,CE);
  637. FTCPE (Q,D,C,CLR,PRE,CE);
  638. LDCP (Q,D,G,CLR,PRE);
  639. ****************************** Device Pin Out *****************************
  640. Device : XC9572XL-5-VQ44
  641. --------------------------------
  642. /44 43 42 41 40 39 38 37 36 35 34 \
  643. | 1 33 |
  644. | 2 32 |
  645. | 3 31 |
  646. | 4 30 |
  647. | 5 XC9572XL-5-VQ44 29 |
  648. | 6 28 |
  649. | 7 27 |
  650. | 8 26 |
  651. | 9 25 |
  652. | 10 24 |
  653. | 11 23 |
  654. \ 12 13 14 15 16 17 18 19 20 21 22 /
  655. --------------------------------
  656. Pin Signal Pin Signal
  657. No. Name No. Name
  658. 1 LED<4> 23 KPR
  659. 2 LED<5> 24 TDO
  660. 3 LED<6> 25 GND
  661. 4 GND 26 VCC
  662. 5 LED<7> 27 KPR
  663. 6 TX 28 KPR
  664. 7 KPR 29 KPR
  665. 8 KPR 30 KPR
  666. 9 TDI 31 KPR
  667. 10 TMS 32 KPR
  668. 11 TCK 33 KPR
  669. 12 KPR 34 KPR
  670. 13 KPR 35 VCC
  671. 14 KPR 36 KPR
  672. 15 VCC 37 KPR
  673. 16 KPR 38 KPR
  674. 17 GND 39 KPR
  675. 18 KPR 40 KPR
  676. 19 KPR 41 LED<0>
  677. 20 XSTALIN 42 LED<1>
  678. 21 HZIN 43 LED<2>
  679. 22 KPR 44 LED<3>
  680. Legend : NC = Not Connected, unbonded pin
  681. PGND = Unused I/O configured as additional Ground pin
  682. TIE = Unused I/O floating -- must tie to VCC, GND or other signal
  683. KPR = Unused I/O with weak keeper (leave unconnected)
  684. VCC = Dedicated Power Pin
  685. GND = Dedicated Ground Pin
  686. TDI = Test Data In, JTAG pin
  687. TDO = Test Data Out, JTAG pin
  688. TCK = Test Clock, JTAG pin
  689. TMS = Test Mode Select, JTAG pin
  690. PROHIBITED = User reserved pin
  691. **************************** Compiler Options ****************************
  692. Following is a list of all global compiler options used by the fitter run.
  693. Device(s) Specified : xc9572xl-5-VQ44
  694. Optimization Method : SPEED
  695. Multi-Level Logic Optimization : ON
  696. Ignore Timing Specifications : OFF
  697. Default Register Power Up Value : LOW
  698. Keep User Location Constraints : ON
  699. What-You-See-Is-What-You-Get : OFF
  700. Exhaustive Fitting : OFF
  701. Keep Unused Inputs : OFF
  702. Slew Rate : FAST
  703. Power Mode : STD
  704. Ground on Unused IOs : OFF
  705. Set I/O Pin Termination : KEEPER
  706. Global Clock Optimization : ON
  707. Global Set/Reset Optimization : ON
  708. Global Ouput Enable Optimization : ON
  709. Input Limit : 54
  710. Pterm Limit : 25