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259 lines
9.9 KiB

4 years ago
  1. Release 14.7 - xst P.20131013 (lin)
  2. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5. Total REAL time to Xst completion: 0.00 secs
  6. Total CPU time to Xst completion: 0.13 secs
  7. -->
  8. Parameter xsthdpdir set to xst
  9. Total REAL time to Xst completion: 0.00 secs
  10. Total CPU time to Xst completion: 0.13 secs
  11. -->
  12. Reading design: counta.prj
  13. TABLE OF CONTENTS
  14. 1) Synthesis Options Summary
  15. 2) HDL Compilation
  16. 3) Design Hierarchy Analysis
  17. 4) HDL Analysis
  18. 5) HDL Synthesis
  19. 5.1) HDL Synthesis Report
  20. 6) Advanced HDL Synthesis
  21. 6.1) Advanced HDL Synthesis Report
  22. 7) Low Level Synthesis
  23. 8) Partition Report
  24. 9) Final Report
  25. =========================================================================
  26. * Synthesis Options Summary *
  27. =========================================================================
  28. ---- Source Parameters
  29. Input File Name : "counta.prj"
  30. Input Format : mixed
  31. Ignore Synthesis Constraint File : NO
  32. ---- Target Parameters
  33. Output File Name : "counta"
  34. Output Format : NGC
  35. Target Device : XC9500XL CPLDs
  36. ---- Source Options
  37. Top Module Name : counta
  38. Automatic FSM Extraction : YES
  39. FSM Encoding Algorithm : Auto
  40. Safe Implementation : No
  41. Mux Extraction : Yes
  42. Resource Sharing : YES
  43. ---- Target Options
  44. Add IO Buffers : YES
  45. MACRO Preserve : YES
  46. XOR Preserve : YES
  47. Equivalent register Removal : YES
  48. ---- General Options
  49. Optimization Goal : Speed
  50. Optimization Effort : 1
  51. Keep Hierarchy : Yes
  52. Netlist Hierarchy : As_Optimized
  53. RTL Output : Yes
  54. Hierarchy Separator : /
  55. Bus Delimiter : <>
  56. Case Specifier : Maintain
  57. Verilog 2001 : YES
  58. ---- Other Options
  59. Clock Enable : YES
  60. wysiwyg : NO
  61. =========================================================================
  62. =========================================================================
  63. * HDL Compilation *
  64. =========================================================================
  65. Compiling vhdl file "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.vhd" in Library work.
  66. Entity <counta> compiled.
  67. Entity <counta> (Architecture <behavioral>) compiled.
  68. =========================================================================
  69. * Design Hierarchy Analysis *
  70. =========================================================================
  71. Analyzing hierarchy for entity <counta> in library <work> (architecture <behavioral>).
  72. =========================================================================
  73. * HDL Analysis *
  74. =========================================================================
  75. Analyzing Entity <counta> in library <work> (Architecture <behavioral>).
  76. Entity <counta> analyzed. Unit <counta> generated.
  77. =========================================================================
  78. * HDL Synthesis *
  79. =========================================================================
  80. Performing bidirectional port resolution...
  81. Synthesizing Unit <counta>.
  82. Related source file is "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.vhd".
  83. WARNING:Xst:1780 - Signal <ORvalforstore> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  84. Found 1-bit register for signal <alreadystoredcnt<0>>.
  85. Found 13-bit up counter for signal <clkcounta>.
  86. Found 1-bit register for signal <resetclk<0>>.
  87. Found 19-bit register for signal <storecounta>.
  88. Found 5-bit up counter for signal <uartctr>.
  89. Found 1-bit register for signal <uartnow<0>>.
  90. Found 1-bit register for signal <uartskip<0>>.
  91. Found 1-bit register for signal <waitnow<0>>.
  92. Summary:
  93. inferred 2 Counter(s).
  94. inferred 22 D-type flip-flop(s).
  95. Unit <counta> synthesized.
  96. =========================================================================
  97. HDL Synthesis Report
  98. Macro Statistics
  99. # Counters : 2
  100. 13-bit up counter : 1
  101. 5-bit up counter : 1
  102. # Registers : 24
  103. 1-bit register : 24
  104. =========================================================================
  105. =========================================================================
  106. * Advanced HDL Synthesis *
  107. =========================================================================
  108. =========================================================================
  109. Advanced HDL Synthesis Report
  110. Macro Statistics
  111. # Counters : 2
  112. 13-bit up counter : 1
  113. 5-bit up counter : 1
  114. # Registers : 22
  115. Flip-Flops : 22
  116. =========================================================================
  117. =========================================================================
  118. * Low Level Synthesis *
  119. =========================================================================
  120. Optimizing unit <counta> ...
  121. implementation constraint: INIT=r : storecounta_10
  122. implementation constraint: INIT=r : storecounta_0
  123. implementation constraint: INIT=r : waitnow_0
  124. implementation constraint: INIT=r : storecounta_11
  125. implementation constraint: INIT=r : storecounta_1
  126. implementation constraint: INIT=r : storecounta_12
  127. implementation constraint: INIT=r : storecounta_2
  128. implementation constraint: INIT=r : storecounta_13
  129. implementation constraint: INIT=r : storecounta_3
  130. implementation constraint: INIT=r : storecounta_14
  131. implementation constraint: INIT=r : storecounta_4
  132. implementation constraint: INIT=r : storecounta_15
  133. implementation constraint: INIT=r : storecounta_5
  134. implementation constraint: INIT=r : storecounta_16
  135. implementation constraint: INIT=r : storecounta_6
  136. implementation constraint: INIT=r : storecounta_17
  137. implementation constraint: INIT=r : storecounta_7
  138. implementation constraint: INIT=r : storecounta_18
  139. implementation constraint: INIT=r : storecounta_8
  140. implementation constraint: INIT=r : storecounta_9
  141. implementation constraint: INIT=r : uartnow_0
  142. implementation constraint: INIT=r : uartskip_0
  143. implementation constraint: INIT=r : alreadystoredcnt_0
  144. implementation constraint: INIT=r : uartctr_2
  145. implementation constraint: INIT=r : resetclk_0
  146. implementation constraint: INIT=r : clkcounta_12
  147. implementation constraint: INIT=r : uartctr_3
  148. implementation constraint: INIT=r : clkcounta_0
  149. implementation constraint: INIT=r : clkcounta_1
  150. implementation constraint: INIT=r : clkcounta_2
  151. implementation constraint: INIT=r : clkcounta_3
  152. implementation constraint: INIT=r : clkcounta_4
  153. implementation constraint: INIT=r : clkcounta_5
  154. implementation constraint: INIT=r : clkcounta_6
  155. implementation constraint: INIT=r : clkcounta_7
  156. implementation constraint: INIT=r : clkcounta_8
  157. implementation constraint: INIT=r : clkcounta_9
  158. implementation constraint: INIT=r : clkcounta_10
  159. implementation constraint: INIT=r : clkcounta_11
  160. implementation constraint: INIT=r : uartctr_4
  161. implementation constraint: INIT=r : uartctr_0
  162. implementation constraint: INIT=r : uartctr_1
  163. =========================================================================
  164. * Partition Report *
  165. =========================================================================
  166. Partition Implementation Status
  167. -------------------------------
  168. No Partitions were found in this design.
  169. -------------------------------
  170. =========================================================================
  171. * Final Report *
  172. =========================================================================
  173. Final Results
  174. RTL Top Level Output File Name : counta.ngr
  175. Top Level Output File Name : counta
  176. Output Format : NGC
  177. Optimization Goal : Speed
  178. Keep Hierarchy : Yes
  179. Target Technology : XC9500XL CPLDs
  180. Macro Preserve : YES
  181. XOR Preserve : YES
  182. Clock Enable : YES
  183. wysiwyg : NO
  184. Design Statistics
  185. # IOs : 11
  186. Cell Usage :
  187. # BELS : 395
  188. # AND2 : 131
  189. # AND3 : 30
  190. # AND4 : 13
  191. # AND5 : 1
  192. # GND : 1
  193. # INV : 156
  194. # OR2 : 45
  195. # OR3 : 1
  196. # OR4 : 1
  197. # XOR2 : 16
  198. # FlipFlops/Latches : 42
  199. # FD : 13
  200. # FDCE : 29
  201. # IO Buffers : 11
  202. # IBUF : 2
  203. # OBUF : 9
  204. =========================================================================
  205. Total REAL time to Xst completion: 10.00 secs
  206. Total CPU time to Xst completion: 10.28 secs
  207. -->
  208. Total memory usage is 165256 kilobytes
  209. Number of errors : 0 ( 0 filtered)
  210. Number of warnings : 1 ( 0 filtered)
  211. Number of infos : 0 ( 0 filtered)