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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  4. use IEEE.NUMERIC_STD.ALL;
  5. --xc9500xl has 5 volt tolerant inputs
  6. entity counta is
  7. --TODO: figure out how to get XSTALIN as GCK (see also fitter report (text))
  8. PORT( XSTALIN : in STD_LOGIC; -- semi colons
  9. HZIN : in STD_LOGIC; -- here
  10. LED : out STD_LOGIC_VECTOR(7 downto 0); -- commas in instance
  11. TX : out STD_LOGIC --last one, no semi colon
  12. );
  13. end counta;
  14. architecture Behavioral of counta is
  15. -- 2 to the power of 20 is about 1million
  16. -- gives me 600KHz resolution. Good enough.
  17. -- any more would run into limitations of cpld.
  18. -- EDIT: ran into limits
  19. -- now trying 12 + 1 bits, or about upper limit of 6,000
  20. --signal
  21. signal clkcounta : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
  22. --signal testhzctr : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
  23. signal storecounta : STD_LOGIC_VECTOR(18 DOWNTO 0) := (others => '0');
  24. signal alreadystoredcnt : STD_LOGIC_VECTOR(0 downto 0) := "0";
  25. signal uartnow : STD_LOGIC_VECTOR(0 downto 0) := "0";
  26. signal uartctr : STD_LOGIC_VECTOR(4 downto 0) := "00000";
  27. signal waitnow : STD_LOGIC_VECTOR(0 downto 0) := "0";
  28. signal resetclk : STD_LOGIC_VECTOR(0 downto 0) := "0";
  29. signal uartskip : STD_LOGIC_VECTOR(0 downto 0) := "0";
  30. signal ORvalforstore : STD_LOGIC_VECTOR(2 downto 0) := "111";
  31. begin
  32. --outside of process
  33. TX <= storecounta(0);
  34. LED(5 downto 0) <= storecounta(12 downto 7);
  35. LED(6) <= uartnow(0);
  36. LED(7) <= waitnow(0);
  37. --sanity check that leds / switch is working
  38. --LED(7) <= switch;
  39. mycounta: process (XSTALIN)
  40. begin
  41. if rising_edge(XSTALIN) then
  42. clkcounta <= clkcounta + 1;
  43. --testing clock
  44. --EDIT: below not necessary, as register is already
  45. -- wrapping around after getting to 255/256
  46. -- if clkcounta > 250 then
  47. -- clkcounta <= (others => '0');
  48. --
  49. -- end if;
  50. --MAIN
  51. --shift value out via uart
  52. --(because this is a 6KHz clock, won't be too fast)
  53. if uartnow(0) = '1' then
  54. storecounta <= '1' & storecounta(18 downto 1); --should be down to 1, not 0
  55. --NOTE: because this goes down to 1, 0 is always low
  56. --which in uart would be start bit, I THINK........
  57. end if;
  58. --upon 1hz trigger, and not stored val yet
  59. -- (1hz trigger, is 1hz square wave)
  60. if HZIN = '1' and alreadystoredcnt(0) = '0' then
  61. --store clk val in register
  62. storecounta(15 downto 3) <= clkcounta;
  63. --don't store it again
  64. alreadystoredcnt(0) <= '1';
  65. --reset counter
  66. resetclk(0) <= '1';
  67. --remember, everything in if statement happens all at once
  68. elsif resetclk(0) = '1' then
  69. clkcounta <= (others => '0');
  70. resetclk(0) <= '0';
  71. --frame bits to identify where i am
  72. storecounta(18) <= '0';
  73. storecounta(17) <= '0';
  74. storecounta(16) <= '1';
  75. --data goes from 3 - 15, 3,4,5,6,7, 8,9,10,11,12, 13,14,15
  76. --12+1 bits
  77. storecounta(0) <= '0';
  78. storecounta(1) <= '0';
  79. storecounta(2) <= '1';
  80. elsif alreadystoredcnt(0) = '1' and waitnow(0) = '0' and uartskip(0) = '0' then
  81. --enable uart
  82. uartnow(0) <= '1';
  83. --without this skip, otherwise we get stuck here
  84. uartskip(0) <= '1';
  85. elsif uartnow(0) = '1' and uartctr(4 downto 0) = "11111" then
  86. --disable uart
  87. uartnow(0) <= '0';
  88. uartctr <= (others => '0');
  89. --don't do this and don't enable uart above, and don't count
  90. waitnow(0) <= '1';
  91. elsif alreadystoredcnt(0) = '1' and waitnow(0) = '0' and uartskip(0) = '1' and uartnow(0) = '1'then
  92. uartctr <= uartctr + 1;
  93. --this must be after the above, otherwise we get stuck in it
  94. elsif HZIN = '0' and alreadystoredcnt(0) = '1' and waitnow(0) = '1' and uartskip(0) = '1' and uartnow(0) = '0' then
  95. --reset storedcounter
  96. alreadystoredcnt(0) <= '0';
  97. --only do this once
  98. storecounta <= (others => '1'); --idle high in uart
  99. waitnow(0) <= '0';
  100. uartskip(0) <= '0';
  101. end if;
  102. --using 6MHz clk
  103. --count as far as possible, every 1 second pulse
  104. --from 60hz divider
  105. --at pulse, display count, then start over
  106. -- if HZIN = '1' and hzinhighflag(0) = '0' then
  107. --display value on leds
  108. --todo
  109. --start counter over
  110. -- clkcounta <= (others => '0');
  111. --don't do anything until hz is low
  112. -- hzinhighflag(0) <= '1';
  113. --end if;
  114. --end if;
  115. --EDIT: cpld has limitations, therefore lowering register sizes
  116. end if; -- main rising clk process end
  117. end process;
  118. end Behavioral;