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4 years ago
  1. -- VHDL Instantiation Created from source file counta.vhd -- 01:07:15 07/14/2020
  2. --
  3. -- Notes:
  4. -- 1) This instantiation template has been automatically generated using types
  5. -- std_logic and std_logic_vector for the ports of the instantiated module
  6. -- 2) To use this template to instantiate this entity, cut-and-paste and then edit
  7. COMPONENT counta
  8. PORT(
  9. XSTALIN : IN std_logic;
  10. HZIN : IN std_logic;
  11. SWITCH : IN std_logic;
  12. LED : OUT std_logic_vector(7 downto 0);
  13. TX : OUT std_logic
  14. );
  15. END COMPONENT;
  16. Inst_counta: counta PORT MAP(
  17. XSTALIN => ,
  18. HZIN => ,
  19. SWITCH => ,
  20. LED => ,
  21. TX =>
  22. );