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<title>CPLD Timing Analysis Glossary</title>
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<h1>Introduction</h1>
<p>This report is the result of a static timing analysis of your design  after it has been fit in the device that you selected. The timing values  given represent the worst-case values over the recommended operating conditions  for the part. </p>
<h1>Overview</h1>
<p>The timing report consists of a series of sections: </p>
<h2>Summary</h2>
<p>This table summarizes the external timing parameters for your device,  including <a href="#tPD"><!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}--></a>,  <a href="#tCO"><!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--></a>,  <a href="#tSU"><!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--></a>,  <a href="#tCYC"><!--kadov_tag{{<ignored>}}-->tCYC<!--kadov_tag{{</ignored>}}--></a>,  and <a href="#fSYSTEM"><!--kadov_tag{{<ignored>}}-->fSYSTEM<!--kadov_tag{{</ignored>}}--></a>.  <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->For a more  detailed description of the timing model for your device, please refer  to the application notes linked below.</p>
<h2>Timing Constraints</h2>
<p>This section reports on any timing constraints that you created for  your design. Timing constraints can be entered using the Constraints Editor  tool, or by editing an Implementation Constraints File directly. For more  information on creating timing constraints, see the Constraints Guide.  </p>
<p class=Note><span style="font-weight: bold;">Note</span> that if you  did not define any constraints for your design, then the timing analysis  software will automatically create a default set of constraints for you.  These include pad-to-pad, register-to-register, pad-to-register, and period  constraints. A constraint value of 0 <!--kadov_tag{{<ignored>}}-->ns<!--kadov_tag{{</ignored>}}-->  will be used for all of these automatically generated constraints. As  a result, all paths listed under each constraint will violate the constraint,  and will have a negative value for slack.</p>
<p class=Note><span style="font-weight: bold;">Note</span> also that to  limit the size of the report, each path endpoint involved in a timing  path will only be listed once, under a single constraint. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
<p>For each timing path listed under a constraint, there is a hyperlink  that can be used to open a window listing the individual internal delay  elements traversed in the path. To understand these delay elements, consult  the <a href="#Definitions">Definitions</a> section below, or the following  application notes and white papers: </p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP375: Understanding  the <!--kadov_tag{{<ignored>}}-->CoolRunner-II<!--kadov_tag{{</ignored>}}-->  Timing Model</a> </p>
<p><a href="http://www.xilinx.com/publications/whitepapers/index.htm">WP122:  Using the <!--kadov_tag{{<ignored>}}-->CoolRunner<!--kadov_tag{{</ignored>}}-->  XPLA3 Timing Model</a> </p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP071: Using  the XC9500 Timing Model</a> </p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP111: Using  the XC9500XL Timing Model</a></p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2"><!--kadov_tag{{<ignored>}}-->XAPP<!--kadov_tag{{</ignored>}}-->  362: Using the XC9500XV Timing Model</a></p>
<p>available in the literature section of <a href="http://www.xilinx.com"><!--kadov_tag{{<ignored>}}-->www.xilinx.com</a>.<!--kadov_tag{{</ignored>}}-->  </p>
<h2>Data Sheet Report</h2>
<p>This section of the report lists the external timing parameters for  your design. This includes; maximum external clock speed for each clock,  setup and hold times for each registered input, clock-to-output pad timing  for each registered output, clock to setup time for each register-to-register  timing path, and pad-to-pad time for each combinatorial path through your  design. </p>
<h2>Going Further</h2>
<p>To do more advanced timing analysis of your design, select the process  <span style="font-weight: bold;">Analyze Post-Fit Static Timing</span>  in <!--kadov_tag{{<ignored>}}-->iSE<!--kadov_tag{{</ignored>}}-->. This  will run <!--kadov_tag{{<ignored>}}-->Xilinx's<!--kadov_tag{{</ignored>}}-->  Timing Analyzer tool interactively. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The  Timing Analyzer provides a powerful, flexible, and easy way to perform  static timing analysis on <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}-->  and <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> designs.  With Timing Analyzer, analysis can be performed immediately after mapping,  placing or routing an <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}-->  design, and after fitting and routing a <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}-->  design. </p>
<p>Timing Analyzer verifies that the delay along a given path or paths  meets specified timing requirements. It organizes and displays data that  allows you to analyze critical paths in a circuit, the cycle time of the  circuit, the delay along any specified <!--kadov_tag{{<ignored>}}-->path(s<!--kadov_tag{{</ignored>}}-->),  and the path with the greatest delay. It also provides a quick analysis  of the effect different speed grades have on the same design. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
<p>Timing Analyzer performs setup and hold checks (skew analysis). It works  with synchronous systems composed of synchronous elements and combinatorial  logic. In synchronous design, Timing Analyzer takes into account all path  delays, including clock-to-out and setup requirements, while calculating  the worst-case timing of the design. </p>
<p>Timing Analyzer creates timing analysis reports based on existing timing  constraints or user specified paths within the program. Timing reports  have a hierarchical browser to quickly jump to different sections of the  reports. Timing paths in reports can be cross probed to synthesis tools  (Exemplar and <!--kadov_tag{{<ignored>}}-->Synplicity<!--kadov_tag{{</ignored>}}-->)  and <!--kadov_tag{{<ignored>}}-->Floorplanner<!--kadov_tag{{</ignored>}}-->.  </p>
<p>There are several ways to issue commands in Timing Analyzer. Timing  Analyzer can be controlled through <!--kadov_tag{{<ignored>}}-->GUI<!--kadov_tag{{</ignored>}}-->  features (menu commands) or its comprehensive macro command language facility.  You can select from menus, click toolbar buttons, type keyboard commands  in the console window, and run macros. </p>
<h1><a name=Definitions></a>Definitions</h1>
<h2><a name=tPD></a>Pad to Pad (<!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}-->)  </h2>
<p>Reports pad to pad paths that start at input pads and end at output  pads. The maximum external pad to pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Combinatorial  pad-to-pad paths begin at input pads, propagate through one or more levels  of combinatorial logic and end at output pads. Combinatorial paths also  trace through the enable inputs of 3-state controlled pads. Combinatorial  paths are not traced through clock, and asynchronous set and reset inputs  of registers. These paths are also broken at bidirectional pins</p>
<h2><a name=tCO></a>Clock Pad to Output Pad (<!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->)  </h2>
<p>The maximum external clock pad to output pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Reports  paths that start at input <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->pads  trace through clock inputs of <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->registers  and end at output pads. Paths are not traced through PRE/<!--kadov_tag{{<ignored>}}-->CLR<!--kadov_tag{{</ignored>}}-->  <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->inputs  of registers. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You  can directly specify <!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->  for all registered output paths in your design using the Pad-to-Pad <!--kadov_tag{{<ignored>}}-->timespec<!--kadov_tag{{</ignored>}}-->.  Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate  through global clock buffers, and propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}-->  output and any number of levels of combinatorial logic and end at the  output pad. Clock-Pad-to-Pad paths for product term clock paths begin  at input pads, propagate through any number of logic levels feeding into  a clock product term, propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}-->  output and any number of levels of combinatorial logic and end at the  output pad. Clock-Pad-to-Pad paths also trace through the enable inputs  of 3-state controlled pads.</p>
<h2><a name=tSU></a>Setup to Clock at Pad (<!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->  or <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) </h2>
<p>Reports external setup time of data <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->to  clock at pad. Data path starts at an input pad and ends at register <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->(Fast  Input Register for <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->)  D/<!--kadov_tag{{<ignored>}}-->T<!--kadov_tag{{</ignored>}}--> <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->input.  Clock path starts at input pad and ends at the register clock input. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Paths  are not traced through registers. Pin-to-pin setup requirement is not  reported or guaranteed for product-term clocks derived from <!--kadov_tag{{<ignored>}}-->macrocell<!--kadov_tag{{</ignored>}}-->  feedback signals. </p>
<p>The minimum required setup time for flip-flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You  can specify the <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->  (setup-to-clock) for all inputs in your design relative to a global clock  or product term clock. Each <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->  OFFSET timespec involves an input path and a clock path. Input paths start  at input pads, propagate through input buffers and any number of combinatorial  logic levels before ending at a flip-flop D/T input, including the receiving  flip-flop's tSU. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Input  paths are not traced through flip-flop clock pins, asynchronous set/reset  inputs or bidirectional I/O pins. Global clock paths start at global clock  pads, propagate through global clock buffers and end at the flip-flop  clock pin. Product term clock paths start at input pads, propagate through  a single level of logic implemented in a clock product term and end at  the flip-flop clock pin.</p>
<h2><a name=tCYC></a>Clock to Setup (tCYC) </h2>
<p>Register to register cycle time. Includes source register tCO and destination  register tSU. </p>
<p class=Note><span style="font-weight: bold;">Note</span> that when the  computed Maximum Clock Speed is limited by tCYC, it is computed assuming  that all registers are rising-edge sensitive. </p>
<h2><a name=fSYSTEM></a>fSYSTEM </h2>
<p>Maximum clock operating frequency. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You  can specify the fSYSTEM (clock frequency or period) for all registered  paths in your design using a Register-to-Register timespec. Register-to-Register  paths begin at flip-flop clock inputs, propagate through the flip-flop  Q output and any number of levels of combinatorial logic and end at the  receiving flip-flop D/T input, including the receiving flip-flop's tSU.  When these flip-flops are clocked by the same clock, the delay on this  path is equivalent to the cycle time of the clock. Registered paths do  not propagate through clock, and asynchronous set and reset inputs of  registers as shown below. These paths are also broken at bidirectional  pins.</p>
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