Release 14.7 - xst P.20131013 (lin) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.13 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.13 secs --> Reading design: counta.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "counta.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "counta" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : counta Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit register for signal >. Found 13-bit up counter for signal . Found 1-bit register for signal >. Found 19-bit register for signal . Found 5-bit up counter for signal . Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Summary: inferred 2 Counter(s). inferred 22 D-type flip-flop(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 2 13-bit up counter : 1 5-bit up counter : 1 # Registers : 24 1-bit register : 24 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Counters : 2 13-bit up counter : 1 5-bit up counter : 1 # Registers : 22 Flip-Flops : 22 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=r : storecounta_10 implementation constraint: INIT=r : storecounta_0 implementation constraint: INIT=r : waitnow_0 implementation constraint: INIT=r : storecounta_11 implementation constraint: INIT=r : storecounta_1 implementation constraint: INIT=r : storecounta_12 implementation constraint: INIT=r : storecounta_2 implementation constraint: INIT=r : storecounta_13 implementation constraint: INIT=r : storecounta_3 implementation constraint: INIT=r : storecounta_14 implementation constraint: INIT=r : storecounta_4 implementation constraint: INIT=r : storecounta_15 implementation constraint: INIT=r : storecounta_5 implementation constraint: INIT=r : storecounta_16 implementation constraint: INIT=r : storecounta_6 implementation constraint: INIT=r : storecounta_17 implementation constraint: INIT=r : storecounta_7 implementation constraint: INIT=r : storecounta_18 implementation constraint: INIT=r : storecounta_8 implementation constraint: INIT=r : storecounta_9 implementation constraint: INIT=r : uartnow_0 implementation constraint: INIT=r : uartskip_0 implementation constraint: INIT=r : alreadystoredcnt_0 implementation constraint: INIT=r : uartctr_2 implementation constraint: INIT=r : resetclk_0 implementation constraint: INIT=r : clkcounta_12 implementation constraint: INIT=r : uartctr_3 implementation constraint: INIT=r : clkcounta_0 implementation constraint: INIT=r : clkcounta_1 implementation constraint: INIT=r : clkcounta_2 implementation constraint: INIT=r : clkcounta_3 implementation constraint: INIT=r : clkcounta_4 implementation constraint: INIT=r : clkcounta_5 implementation constraint: INIT=r : clkcounta_6 implementation constraint: INIT=r : clkcounta_7 implementation constraint: INIT=r : clkcounta_8 implementation constraint: INIT=r : clkcounta_9 implementation constraint: INIT=r : clkcounta_10 implementation constraint: INIT=r : clkcounta_11 implementation constraint: INIT=r : uartctr_4 implementation constraint: INIT=r : uartctr_0 implementation constraint: INIT=r : uartctr_1 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : counta.ngr Top Level Output File Name : counta Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 11 Cell Usage : # BELS : 395 # AND2 : 131 # AND3 : 30 # AND4 : 13 # AND5 : 1 # GND : 1 # INV : 156 # OR2 : 45 # OR3 : 1 # OR4 : 1 # XOR2 : 16 # FlipFlops/Latches : 42 # FD : 13 # FDCE : 29 # IO Buffers : 11 # IBUF : 2 # OBUF : 9 ========================================================================= Total REAL time to Xst completion: 10.00 secs Total CPU time to Xst completion: 10.28 secs --> Total memory usage is 165256 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered)