# Xilinx Design Summary

counta Project Status (07/14/2020 - 01:00:23)
Project File: | cpld_countertest10.xise | Parser Errors: | No Errors
Module Name: | counta | Implementation State: | Fitted

Target Device:

xc9572xl-5VQ44

- Errors:

No Errors

Product Version:

ISE 14.7

- Warnings:

1 Warning (0 new)

Design Goal:</dif>

Balanced

- Routing Results:

Design Strategy:</dif>

Xilinx Default (unlocked)

- Timing Constraints:

Environment:</dif>

System Settings

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Tue Aug 4 00:40:22 2020 | 0 | 1 Warning (0 new) | 0
Translation Report | Current | Tue Aug 4 00:40:37 2020 | 0 | 0 | 0
CPLD Fitter Report (Text) | Current | Tue Aug 4 00:40:42 2020 |  |  |
Power Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
Post-Fit Simulation Model Report |  |

Date Generated: 08/04/2020 - 00:49:24