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+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work.
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin.
+
+\textbf{Problems:} The timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. This is likely because I quickly prototyped with digitalRead. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display}
+I've 
+
+
+\section{Project Rev A Complete}
+After another night or two of work, I have a working prototype. 
+
+
+\end{document}
+
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+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work.
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin.
+
+\textbf{Problems:} The timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. This is likely because I quickly prototyped with digitalRead. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+
+\end{verbatim}
+
+may fix these issues.
+
+\section{Project Rev A Complete}
+After another night or two of work, I have a working prototype. 
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/16.toc b/60hz_Divider/docs/16.toc
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+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{4}
+\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}
+\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display}{6}
+\contentsline {section}{\numberline {2}Project Rev A Complete}{6}
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+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work.
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin.
+
+\textbf{Problems:} The timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. This is likely because I quickly prototyped with digitalRead. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\section{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/17.tex~ b/60hz_Divider/docs/17.tex~
new file mode 100644
index 0000000..d4775f8
--- /dev/null
+++ b/60hz_Divider/docs/17.tex~
@@ -0,0 +1,140 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work.
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin.
+
+\textbf{Problems:} The timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. This is likely because I quickly prototyped with digitalRead. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display}
+I've 
+
+
+\section{Project Rev A Complete}
+After another night or two of work, I have a working prototype. 
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/17.toc b/60hz_Divider/docs/17.toc
new file mode 100644
index 0000000..1e16e0a
--- /dev/null
+++ b/60hz_Divider/docs/17.toc
@@ -0,0 +1,12 @@
+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{5}
+\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}
+\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display via Uno}{6}
+\contentsline {section}{\numberline {2}Project Rev A Complete}{7}
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+\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}}
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diff --git a/60hz_Divider/docs/18.pdf b/60hz_Divider/docs/18.pdf
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diff --git a/60hz_Divider/docs/18.tex b/60hz_Divider/docs/18.tex
new file mode 100644
index 0000000..e8d0c38
--- /dev/null
+++ b/60hz_Divider/docs/18.tex
@@ -0,0 +1,195 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+Back to the 14 bit stream...
+
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
+
+\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\section{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/18.tex~ b/60hz_Divider/docs/18.tex~
new file mode 100644
index 0000000..0871cff
--- /dev/null
+++ b/60hz_Divider/docs/18.tex~
@@ -0,0 +1,191 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work.
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin.
+
+\textbf{Problems:} The timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. This is likely because I quickly prototyped with digitalRead. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\section{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/18.toc b/60hz_Divider/docs/18.toc
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+++ b/60hz_Divider/docs/18.toc
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+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{5}
+\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}
+\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display via Uno}{6}
+\contentsline {section}{\numberline {2}Project Rev A Complete}{7}
diff --git a/60hz_Divider/docs/19.aux b/60hz_Divider/docs/19.aux
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+++ b/60hz_Divider/docs/19.aux
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+\relax 
+\@writefile{toc}{\contentsline {section}{\numberline {1}60Hz Divider}{1}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Overview}{1}}
+\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces 60 Hz Logic Divider to 1Hz\relax }}{2}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}}
+\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.\relax }}{4}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{5}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display via Uno}{6}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.9}Project Rev A Complete}{7}}
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diff --git a/60hz_Divider/docs/19.pdf b/60hz_Divider/docs/19.pdf
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+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+Back to the 14 bit stream...
+
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
+
+\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\subsection{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/19.tex~ b/60hz_Divider/docs/19.tex~
new file mode 100644
index 0000000..e8d0c38
--- /dev/null
+++ b/60hz_Divider/docs/19.tex~
@@ -0,0 +1,195 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+Back to the 14 bit stream...
+
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
+
+\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\section{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/19.toc b/60hz_Divider/docs/19.toc
new file mode 100644
index 0000000..ae76a37
--- /dev/null
+++ b/60hz_Divider/docs/19.toc
@@ -0,0 +1,12 @@
+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{5}
+\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}
+\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display via Uno}{6}
+\contentsline {subsection}{\numberline {1.9}Project Rev A Complete}{7}
diff --git a/60hz_Divider/docs/20.aux b/60hz_Divider/docs/20.aux
new file mode 100644
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--- /dev/null
+++ b/60hz_Divider/docs/20.aux
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+\@writefile{toc}{\contentsline {section}{\numberline {1}60Hz Divider}{1}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Overview}{1}}
+\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces 60 Hz Logic Divider to 1Hz\relax }}{1}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}}
+\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.\relax }}{4}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{4}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}}
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+\@writefile{toc}{\contentsline {subsection}{\numberline {1.9}Project Rev A Complete}{7}}
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diff --git a/60hz_Divider/docs/20.tex b/60hz_Divider/docs/20.tex
new file mode 100644
index 0000000..52047fd
--- /dev/null
+++ b/60hz_Divider/docs/20.tex
@@ -0,0 +1,195 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+Back to the 14 bit stream...
+
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
+
+\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\subsection{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+%todo insert picture
+
+\end{document}
+
diff --git a/60hz_Divider/docs/20.tex~ b/60hz_Divider/docs/20.tex~
new file mode 100644
index 0000000..5defbdb
--- /dev/null
+++ b/60hz_Divider/docs/20.tex~
@@ -0,0 +1,195 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+\subsection{Parsing of CPLD UART Stream}
+Back to the 14 bit stream...
+
+I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
+
+\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
+
+\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
+
+\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
+
+\begin{verbatim}
+Example Code Snippet
+
+Let's demonstrate the use of the DDRx, 
+PORTx and PINx registers from the
+ following code snippet:
+
+DDRC = 0x0F;
+PORTC = 0x0C;
+
+// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
+if (PINC == 0b01000000)
+    PORTC = 0x0B;
+else
+    PORTC = 0x00;
+\end{verbatim}
+Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
+
+
+may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}. 
+\subsection{Max7219 8 digit 7-Segment Display via Uno}
+I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
+
+\begin{verbatim}
+//https://playground.arduino.cc/Main/LedControl/#Seg7Control
+void printNumber(int v) {
+    int ones;
+    int tens;
+    int hundreds;
+    int thousands;
+    boolean negative;  
+
+    if(v < -9999 || v > 9999) 
+       return;
+    if(v<0) {
+        negative=true;
+        v=v*-1;
+    }
+    ones=v%10;
+    v=v/10;
+    tens=v%10;
+    v=v/10;
+    hundreds=v%10;
+    v=v/10;
+    thousands=v;     
+    /*if(negative) {
+       //print character '-' in the leftmost column 
+       lc.setChar(0,4,'-',false);
+    }
+    else {
+       //print a blank in the sign column
+       lc.setChar(0,4,' ',false);
+    }*/
+    //Now print the number digit by digit
+    lc.setDigit(0,3,(byte)thousands,false);
+    lc.setDigit(0,2,(byte)hundreds,false);
+    lc.setDigit(0,1,(byte)tens,false);
+    lc.setDigit(0,0,(byte)ones,false);
+}
+\end{verbatim}
+Note that I commented out the negative sign on this. My values are always positive.
+
+
+
+\subsection{Project Rev A Complete}
+With the above complete, I have an initial prototype. The issues with this are the following:
+
+\begin{itemize}
+\item Uno reads 14 bit serial stream wrong (timing issues)
+\item 7 segment display slightly bright
+  \item Should add readout of 120 Volts (can get from transformer)
+  \item Plywood should be replaced with fiberglass
+\end{itemize}
+
+It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
+
+Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
+
+
+
+
+\end{document}
+
diff --git a/60hz_Divider/docs/20.toc b/60hz_Divider/docs/20.toc
new file mode 100644
index 0000000..ca0f002
--- /dev/null
+++ b/60hz_Divider/docs/20.toc
@@ -0,0 +1,12 @@
+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{4}
+\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}
+\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display via Uno}{6}
+\contentsline {subsection}{\numberline {1.9}Project Rev A Complete}{7}
diff --git a/Log_Viewer/docs/5.log b/Log_Viewer/docs/5.log
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new file mode 100644
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+\relax 
+\@writefile{toc}{\contentsline {section}{\numberline {1}Log Viewer}{1}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}LM317}{1}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Power Board}{2}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.2.1}Video Output Modes}{2}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}Misc Notes}{3}}
diff --git a/Log_Viewer/docs/6.log b/Log_Viewer/docs/6.log
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diff --git a/Log_Viewer/docs/6.pdf b/Log_Viewer/docs/6.pdf
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+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{Log Viewer}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+\maketitle
+
+%\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{Log Viewer}}
+
+
+\subsection{LM317}
+As the viewfinder needs its own power supply, I need 7V from 12V. Parts box has LM317.
+
+\begin{verbatim}
+Formula for LM317:
+     Vout = 1.25 * (1+ R2/R1)
+
+           R1 = vout to gndpin
+           R2 = gndpin to gnd
+
+           e.g. 720 R2, 240 R1 == 5V
+                1K R2 == 6.45V
+                1.1K R2 == 6.97V
+                
+\end{verbatim}
+\textbf{Standard R1 is 240ohm}, so let's keep to the standard.\footnote{Check when looking through devices that use LM317, which adhere to that standard. They should, when possible. Standards should always be followed.}
+\\
+\\
+Make sure to \underline{account for the drop out} needed for Vin to LM317.
+
+
+
+\textcolor{green!60!blue!70}{
+  \subsection{Power Board}}
+\emph{Cutting dip switches in half, because they don't sell smaller than arrays of 4.}
+
+
+I built an adapter board. LM317, with svideo out signal split. There are two signals on svideo, and two grounds. The signals, can be viewed in a scope. Y and C. One is video (Y - Luminance and Sync). The other, doesn't look like ntsc video (chroma), and is put in series w/470pf cap to the video signal. Be careful that the picture is of the male connector, not female. Review signals in scope to be sure. If you get it backwards, as I did, it probably won't break anything.
+\footnote{Ref: https://www.linuxtv.org/wiki/index.php/Composite\_to\_S-Video}
+
+\textcolor{green!60!blue!70}{
+\subsubsection{Video Output Modes}}
+At this point, with the Beagleboard, I have video outputting to the CRT but not at the right resolution. Hwinfo --framebuffer is empty on beagleboard (when X is not running). Seems the fb is not enabled.
+
+I looked at a lot of information. There are some sources advising changing kernel flags (touchy, may cause failure to boot), i.e. vga=\#\#\# where number is a reference to the resolution (there is a LUT, it's not 1:1). However none of that looked like the right path...
+
+The man page of console-setup explains, different fonts have different font sizes. I tried the largest FIXED font at first, but it wasn't enough. After reading the man, I changed to TerminusBold, which had larger fonts. This seems to work.\footnote{Edges of screen are still a bit hard to see in crt. I will look for a work around once I'm logged in.}
+
+One thing, my main keyboard doesn't work on the bb (via usb A). Need a different one. Instead, I should change from the ssh'd terminal to the svideo. Magic search term here is maybe: ``linux ssh to local tty'' Appears that screen (for existing logged in sessions) or linuxvnc is an option. Might be difficult if I'm not already logged in. EDIT: linuxvnc is obsolete.
+
+These look like the solution
+https://raspberrypi.stackexchange.com/questions/50220/connect-the-tty1-screen-to-my-ssh-session
+https://www.linuxquestions.org/questions/linux-general-1/ssh-to-local-console-tty-576349/
+
+It's something I've already done: have user auto logged in, then jump onto the session afterwards. Easy.
+
+\subsection{Misc Notes}
+\begin{verbatim}
+switch matrix via usb, bb, viewfinder.
+hit switch, it changes modes, lights LED
+different modes for e.g.
+1. dl and view logs, rotate through logs by pressing switches (for page down), just cat all logs
+    in folder. (EDIT: less requires two key presses to get to next page (:n), so use more (not less)
+    , and hit space bar)
+2. view irc chat (will need to be connected, so tmux attach, 
+    then use other switches on matrix, to change to next irc chatroom) (ctrl-n)
+3. ????
+
+usb to ethernet, bb, svideo to svideo to viewfinder, switches, etc...
+start small:
+
+    0. expand size of layoutdev hdd - DONE
+    0.1 copy existing bb devuan sd to new img, and new sd card - DONE
+    0.2 lm317 for 7v supply to crt viewfinder. (note: on semi lm317 had smaller to220 tab) DONE
+    1. bb to viewfinder. DONE
+    2. boot into session
+    3. have session w/different scripts that can run
+\end{verbatim}
+
+\end{document}
+