diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/_ngo/netlist.lst b/60hz_Divider/code/xilinx/cpld_countertest10/_ngo/netlist.lst
new file mode 100644
index 0000000..46cc0ce
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/_ngo/netlist.lst
@@ -0,0 +1,2 @@
+/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.ngc 1596516022
+OK
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/ngdbuild.xmsgs b/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/ngdbuild.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/ngdbuild.xmsgs
@@ -0,0 +1,9 @@
+
+
+
+
+
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/pn_parser.xmsgs b/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..db535de
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+Parsing VHDL file "/home/dev/Desktop/code/xilinx/file/cpld_countertest10/counta.vhd" into library work
+
+
+
+
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/xst.xmsgs b/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..ad486db
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/_xmsgs/xst.xmsgs
@@ -0,0 +1,12 @@
+
+
+
+Signal <ORvalforstore> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+
+
+
+
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/constraints.ucf b/60hz_Divider/code/xilinx/cpld_countertest10/constraints.ucf
new file mode 100644
index 0000000..f4c35da
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/constraints.ucf
@@ -0,0 +1,16 @@
+NET "XSTALIN" LOC="P20" ; #should be using bufg=clk
+NET "HZIN" LOC="P21" ;
+NET LED(0) LOC="P41" ;
+NET LED(1) LOC="P42" ;
+NET LED(2) LOC="P43" ;
+NET LED(3) LOC="P44" ;
+NET LED(4) LOC="P1" ;
+NET LED(5) LOC="P2" ;
+NET LED(6) LOC="P3" ;
+NET LED(7) LOC="P5" ;
+NET "TX" LOC="P6" ;
+#NET SWITCH LOC="P18";
+
+#for dangerous prototypes board,
+# led is 38 / 39
+# button is 18
\ No newline at end of file
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.bld b/60hz_Divider/code/xilinx/cpld_countertest10/counta.bld
new file mode 100644
index 0000000..7591f73
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.bld
@@ -0,0 +1,36 @@
+Release 14.7 ngdbuild P.20131013 (lin)
+Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
+
+Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle
+ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+
+Reading NGO file
+"/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.ngc" ...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "constraints.ucf" ...
+Resolving constraint associations...
+Checking Constraint Associations...
+Done...
+
+Checking expanded design ...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Total memory usage is 102216 kilobytes
+
+Writing NGD file "counta.ngd" ...
+Total REAL time to NGDBUILD completion: 7 sec
+Total CPU time to NGDBUILD completion: 7 sec
+
+Writing NGDBUILD log file "counta.bld"...
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.cmd_log b/60hz_Divider/code/xilinx/cpld_countertest10/counta.cmd_log
new file mode 100644
index 0000000..0583624
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.cmd_log
@@ -0,0 +1,383 @@
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/xl9500CPLD_testCounter/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest2/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest4/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+vhdtdtfi -prj cpld_countertest5 -o /home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.vhi -module counta -template /opt/Xilinx/14.7/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror -lib work counta.vhd
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest5/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
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+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
+xst -intstyle ise -ifn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.xst" -ofn "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.syr"
+ngdbuild -intstyle ise -dd _ngo -uc constraints.ucf -p xc9572xl-VQ44-5 counta.ngc counta.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper counta.ngd
+XSLTProcess counta_build.xml
+tsim -intstyle ise counta counta.nga
+hprep6 -s IEEE1149 -n counta -i counta
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.gyd b/60hz_Divider/code/xilinx/cpld_countertest10/counta.gyd
new file mode 100644
index 0000000..8cec0dd
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.gyd
@@ -0,0 +1,37 @@
+Pin Freeze File: version P.20131013
+
+9572XL44VQ XC9572XL-5-VQ44
+HZIN S:PIN21
+XSTALIN S:PIN20
+TX S:PIN6
+LED<0> S:PIN41
+LED<1> S:PIN42
+LED<2> S:PIN43
+LED<3> S:PIN44
+LED<4> S:PIN1
+LED<5> S:PIN2
+LED<6> S:PIN3
+LED<7> S:PIN5
+
+
+;The remaining section of the .gyd file is for documentation purposes only.
+;It shows where your internal equations were placed in the last successful fit.
+
+PARTITION FB1_5 EXP6_ storecounta<7> EXP7_ storecounta<8>
+ storecounta<9> EXP8_ storecounta<10> EXP9_
+ EXP10_ storecounta<11> storecounta<12> EXP11_
+ uartnow<0>
+
+PARTITION FB2_1 EXP12_
+PARTITION FB2_8 clkcounta<9> clkcounta<8> clkcounta<7> clkcounta<6>
+ clkcounta<5> clkcounta<4> clkcounta<3> clkcounta<12>
+ clkcounta<11> clkcounta<10> storecounta<13>
+PARTITION FB3_1 alreadystoredcnt<0> waitnow<0> uartskip<0> clkcounta<0>
+ storecounta<0> uartctr<4> uartctr<3> uartctr<2>
+ uartctr<1> uartctr<0> clkcounta<2> clkcounta<1>
+ storecounta<2> storecounta<1> resetclk<0> storecounta<5>
+ storecounta<4> storecounta<3>
+PARTITION FB4_1 storecounta<14> EXP13_
+PARTITION FB4_12 EXP14_ storecounta<18> storecounta<17> storecounta<16>
+ EXP15_ storecounta<6> storecounta<15>
+
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.jed b/60hz_Divider/code/xilinx/cpld_countertest10/counta.jed
new file mode 100644
index 0000000..5d1d5a6
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.jed
@@ -0,0 +1,1667 @@
+Programmer Jedec Bit Map
+Date Extracted: Tue Aug 4 00:40:50 2020
+
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+L0042368 00000000 00000000 00000000 00000000*
+L0042400 00000000 00000000 00000000 00000000*
+L0042432 00000000 00000000 00000000 00000000*
+L0042464 00000000 00000000 00000000 00000000*
+L0042496 00000000 00000000 00000000 00000000*
+L0042528 00000000 00000000 00000000 00000000*
+L0042560 00000000 00000000 00000000 00000000*
+L0042592 00000000 00000000 00000000 00000000*
+L0042624 000000 000000 000000 000000*
+L0042648 000000 000000 000000 000000*
+L0042672 000000 000000 000000 000000*
+L0042696 000000 000000 000000 000000*
+L0042720 000000 000000 000000 000000*
+L0042744 000000 000000 000000 000000*
+L0042768 00000000 00000000 00000000 00000000*
+L0042800 00000000 00000000 00000000 00000000*
+L0042832 00000000 00000000 00000000 00000000*
+L0042864 00000000 00000000 00000000 00000000*
+L0042896 00000000 00000000 00000000 00000000*
+L0042928 00000000 00000000 00000000 00000000*
+L0042960 00000000 00000000 00000000 00000000*
+L0042992 00000000 00000000 00000000 00000000*
+L0043024 00000000 00000000 00000000 00000000*
+L0043056 000000 000000 000000 000000*
+L0043080 000000 000000 000000 000000*
+L0043104 000000 000000 000000 000000*
+L0043128 000000 000000 000000 000000*
+L0043152 000000 000000 000000 000000*
+L0043176 000000 000000 000000 000000*
+L0043200 00000000 00000000 00000000 00000000*
+L0043232 00000000 00000000 00000000 00000000*
+L0043264 00000000 00000000 00000000 00000000*
+L0043296 00000000 00000000 00000000 00000000*
+L0043328 00000000 00000000 00000000 00000000*
+L0043360 00000000 00000000 00000000 00000000*
+L0043392 00000000 00000000 00000000 00000000*
+L0043424 00000000 00000000 00000000 00000000*
+L0043456 00000000 00000000 00000000 00000000*
+L0043488 000000 000000 000000 000000*
+L0043512 000000 000000 000000 000000*
+L0043536 000000 000000 000000 000000*
+L0043560 000000 000000 000000 000000*
+L0043584 000000 000000 000000 000000*
+L0043608 000000 000000 000000 000000*
+L0043632 00000000 00000000 00000000 00000000*
+L0043664 00000000 00000000 00000000 00000000*
+L0043696 00000000 00000000 00000000 00000000*
+L0043728 00000000 00000000 00000000 00000000*
+L0043760 00000000 00000000 00000000 00000000*
+L0043792 00000000 00000000 00000000 00000000*
+L0043824 00000000 00000000 00000000 00000000*
+L0043856 00000000 00000000 00000000 00000000*
+L0043888 00000000 00000000 00000000 00000000*
+L0043920 000000 000000 000000 000000*
+L0043944 000000 000000 000000 000000*
+L0043968 000000 000000 000000 000000*
+L0043992 000000 000000 000000 000000*
+L0044016 000000 000000 000000 000000*
+L0044040 000000 000000 000000 000000*
+L0044064 00100000 00000000 00000000 00000000*
+L0044096 00001100 10000000 01110000 00001100*
+L0044128 00000000 00000000 00110000 00001000*
+L0044160 00010000 00011100 01110000 00000000*
+L0044192 00000000 00000000 10001000 10001000*
+L0044224 00000000 00000000 00000000 00000000*
+L0044256 00000100 00000000 11101000 00001000*
+L0044288 00000100 00000000 11101000 00001000*
+L0044320 00000100 00111100 10100000 10000000*
+L0044352 000001 000000 100000 000000*
+L0044376 000000 000000 000000 000000*
+L0044400 000100 000000 111100 000000*
+L0044424 000000 000000 111100 000100*
+L0044448 000000 001110 011000 000000*
+L0044472 001000 000000 001011 000000*
+L0044496 00000000 00000000 00000000 00000000*
+L0044528 00000000 00011100 00001000 00000000*
+L0044560 00000000 00011100 00000000 00000000*
+L0044592 00000000 00000000 00001000 00000000*
+L0044624 00000000 00000000 00000000 00000000*
+L0044656 00000000 00000000 00000000 00000000*
+L0044688 00000000 00111100 00010000 00000000*
+L0044720 00000000 00111100 00010000 00000000*
+L0044752 00000000 00000000 00000000 00000000*
+L0044784 000000 000000 000000 000000*
+L0044808 000000 000000 000000 000000*
+L0044832 000000 001110 000000 000010*
+L0044856 000000 001110 000000 000000*
+L0044880 000000 000000 000000 000000*
+L0044904 000000 000000 000000 000010*
+L0044928 00000000 00000000 00000000 00000000*
+L0044960 00000000 00000000 00000000 00000000*
+L0044992 00000000 00000000 00000000 00000000*
+L0045024 00000000 00000000 00000000 00000000*
+L0045056 00000000 00000000 00000000 00000000*
+L0045088 00000000 00000000 00000000 00000000*
+L0045120 00000000 00000000 00000000 00000000*
+L0045152 00000000 00000000 00000000 00000000*
+L0045184 00000000 00000000 00000000 00000000*
+L0045216 000000 000000 000000 000000*
+L0045240 000000 000000 000000 000000*
+L0045264 000000 000000 000000 000000*
+L0045288 000000 000000 000000 000000*
+L0045312 000000 000000 000000 000000*
+L0045336 000000 000000 000000 000000*
+L0045360 00000000 00000000 00000000 00000000*
+L0045392 00000000 00000000 00000000 00000000*
+L0045424 00000000 00000000 10001000 00000000*
+L0045456 00000000 00000000 10000000 00000000*
+L0045488 00000000 00000000 00000000 00000000*
+L0045520 00000000 00000000 00000000 00000000*
+L0045552 00010000 00000000 00000000 00000000*
+L0045584 00000000 00000000 00000000 00000000*
+L0045616 00000000 00000000 00000000 00000000*
+L0045648 000000 000000 000000 000000*
+L0045672 000000 000000 000000 000000*
+L0045696 000000 000000 000000 000000*
+L0045720 000000 000000 000000 000000*
+L0045744 000000 000000 000000 000000*
+L0045768 000000 000000 000000 000000*
+L0045792 00000000 00000000 00000000 00000000*
+L0045824 00000000 00000000 00000000 00000000*
+L0045856 00000000 00000000 00000000 00000000*
+L0045888 00000000 00000000 00000000 00000000*
+L0045920 00000000 00000000 00000000 00000000*
+L0045952 00000000 00000000 00000000 00000000*
+L0045984 00000000 00000000 00000000 00000000*
+L0046016 00000000 00000000 00000000 00000000*
+L0046048 00000000 00000000 00000000 00000000*
+L0046080 000000 000000 000000 000000*
+L0046104 000000 000000 000000 000000*
+L0046128 000000 000000 000000 000000*
+L0046152 000000 000000 000000 000000*
+L0046176 000000 000000 000000 000000*
+L0046200 000000 000000 000000 000000*
+L0046224 00000000 10000000 00000000 00000000*
+L0046256 00000000 00000000 00000000 10000000*
+L0046288 00000000 00000000 00000000 10000000*
+L0046320 00000000 00000000 00000000 10000000*
+L0046352 00000000 00000000 00000000 00000000*
+L0046384 00000000 00000000 00000000 00000000*
+L0046416 00000000 00000000 00000000 00000000*
+L0046448 00000000 00000000 00000000 00000000*
+L0046480 00000000 00000000 00000000 00000000*
+L0046512 000000 000000 000000 000000*
+L0046536 000000 000000 000000 000000*
+L0046560 000000 000000 000000 000000*
+L0046584 000010 000000 000000 000000*
+L0046608 000010 000000 000000 000000*
+L0046632 000000 000001 000000 000001*
+CA81E*
+CAB0
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.lso b/60hz_Divider/code/xilinx/cpld_countertest10/counta.lso
new file mode 100644
index 0000000..b8f99f5
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.lso
@@ -0,0 +1 @@
+work
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.mfd b/60hz_Divider/code/xilinx/cpld_countertest10/counta.mfd
new file mode 100644
index 0000000..ec6030c
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.mfd
@@ -0,0 +1,913 @@
+MDF Database: version 1.0
+MDF_INFO | counta | XC9572XL-5-VQ44
+MACROCELL | 2 | 1 | waitnow<0>
+ATTRIBUTES | 4588322 | 0
+OUTPUTMC | 27 | 2 | 1 | 0 | 16 | 0 | 9 | 0 | 12 | 0 | 11 | 2 | 3 | 0 | 6 | 3 | 15 | 0 | 15 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 11 | 2 | 12 | 2 | 11 | 2 | 5 | 1 | 0 | 2 | 17 | 3 | 1 | 3 | 13 | 3 | 12 | 0 | 8 | 2 | 0 | 2 | 14 | 3 | 0
+INPUTS | 12 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | HZIN | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | XSTALIN
+INPUTMC | 10 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 0
+EQ | 11 |
+ LED<7>.T = LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+ # !LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & uartctr<0> & uartctr<1> &
+ uartctr<2> & uartctr<3> & uartctr<4>
+ # !LED<7> & LED<6> & !alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4> & !HZIN;
+ LED<7>.CLK = XSTALIN;
+ waitnow<0>.EXP = LED<7> & !LED<6> & !resetclk<0> & uartskip<0> &
+ !HZIN
+
+MACROCELL | 0 | 16 | uartnow<0>
+ATTRIBUTES | 4588322 | 0
+OUTPUTMC | 41 | 2 | 1 | 0 | 16 | 0 | 10 | 0 | 13 | 0 | 14 | 0 | 5 | 0 | 7 | 0 | 8 | 1 | 0 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 12 | 2 | 13 | 2 | 12 | 2 | 5 | 1 | 17 | 3 | 0 | 3 | 17 | 3 | 14 | 3 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 3 | 16 | 2 | 4 | 0 | 4 | 0 | 6 | 0 | 9 | 0 | 11 | 0 | 12 | 0 | 15 | 2 | 0 | 2 | 3 | 2 | 11 | 2 | 14 | 3 | 1 | 3 | 11 | 3 | 15
+INPUTS | 12 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | HZIN | XSTALIN
+INPUTMC | 10 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTP | 2 | 65 | 63
+EQ | 12 |
+ LED<6>.T = !LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & !uartskip<0>
+ # LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+ # LED<6> & alreadystoredcnt<0> & !resetclk<0> &
+ uartskip<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+ # LED<6> & !alreadystoredcnt<0> & !resetclk<0> &
+ uartctr<0> & uartctr<1> & uartctr<2> & uartctr<3> &
+ uartctr<4> & !HZIN;
+ LED<6>.CLK = XSTALIN;
+
+MACROCELL | 0 | 10 | storecounta<10>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 3 | 0 | 10 | 0 | 8 | 0 | 11
+INPUTS | 8 | LED<6> | LED<4> | alreadystoredcnt<0> | HZIN | clkcounta<7> | LED<3> | EXP9_.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 0 | 13 | 2 | 0 | 1 | 9 | 0 | 10 | 0 | 11
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 0 | 11
+EQ | 9 |
+ LED<3>.D = LED<6> & LED<4> & alreadystoredcnt<0>
+ # LED<6> & LED<4> & !HZIN
+ # !LED<6> & LED<3> & alreadystoredcnt<0>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<7>
+;Imported pterms FB1_12
+ # !LED<6> & LED<3> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ LED<3>.CLK = XSTALIN;
+
+MACROCELL | 0 | 13 | storecounta<11>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 3 | 0 | 10 | 0 | 13 | 0 | 12
+INPUTS | 8 | LED<6> | LED<5> | alreadystoredcnt<0> | HZIN | clkcounta<8> | LED<4> | EXP10_.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 0 | 14 | 2 | 0 | 1 | 8 | 0 | 13 | 0 | 12
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 0 | 12
+EQ | 9 |
+ LED<4>.D = LED<6> & LED<5> & alreadystoredcnt<0>
+ # LED<6> & LED<5> & !HZIN
+ # !LED<6> & LED<4> & alreadystoredcnt<0>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<8>
+;Imported pterms FB1_13
+ # !LED<6> & LED<4> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ LED<4>.CLK = XSTALIN;
+
+MACROCELL | 0 | 14 | storecounta<12>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 3 | 0 | 13 | 0 | 14 | 0 | 15
+INPUTS | 8 | LED<6> | alreadystoredcnt<0> | storecounta<13> | HZIN | clkcounta<9> | LED<5> | EXP11_.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 2 | 0 | 1 | 17 | 1 | 7 | 0 | 14 | 0 | 15
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 0 | 15
+EQ | 9 |
+ LED<5>.D = LED<6> & alreadystoredcnt<0> & storecounta<13>
+ # LED<6> & storecounta<13> & !HZIN
+ # !LED<6> & LED<5> & alreadystoredcnt<0>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<9>
+;Imported pterms FB1_16
+ # !LED<6> & LED<5> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ LED<5>.CLK = XSTALIN;
+
+MACROCELL | 0 | 5 | storecounta<7>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 3 | 0 | 5 | 3 | 16 | 0 | 4
+INPUTS | 9 | LED<6> | LED<1> | alreadystoredcnt<0> | HZIN | clkcounta<4> | LED<0> | EXP6_.EXP | EXP7_.EXP | XSTALIN
+INPUTMC | 7 | 0 | 16 | 0 | 7 | 2 | 0 | 1 | 12 | 0 | 5 | 0 | 4 | 0 | 6
+INPUTP | 2 | 65 | 63
+IMPORTS | 2 | 0 | 4 | 0 | 6
+EQ | 10 |
+ LED<0>.D = LED<6> & LED<1> & alreadystoredcnt<0>
+ # LED<6> & LED<1> & !HZIN
+ # !LED<6> & LED<0> & alreadystoredcnt<0>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<4>
+;Imported pterms FB1_5
+ # !LED<6> & LED<0> & !HZIN
+;Imported pterms FB1_7
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ LED<0>.CLK = XSTALIN;
+
+MACROCELL | 0 | 7 | storecounta<8>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 3 | 0 | 5 | 0 | 7 | 0 | 8
+INPUTS | 8 | LED<6> | LED<2> | alreadystoredcnt<0> | HZIN | clkcounta<5> | LED<1> | storecounta<9>.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 0 | 8 | 2 | 0 | 1 | 11 | 0 | 7 | 0 | 8
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 0 | 8
+EQ | 9 |
+ LED<1>.D = LED<6> & LED<2> & alreadystoredcnt<0>
+ # LED<6> & LED<2> & !HZIN
+ # !LED<6> & LED<1> & alreadystoredcnt<0>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<5>
+;Imported pterms FB1_9
+ # !LED<6> & LED<1> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ LED<1>.CLK = XSTALIN;
+
+MACROCELL | 0 | 8 | storecounta<9>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 2 | 0 | 7 | 0 | 9
+INPUTS | 10 | LED<6> | LED<3> | alreadystoredcnt<0> | HZIN | LED<1> | LED<7> | resetclk<0> | uartskip<0> | EXP8_.EXP | XSTALIN
+INPUTMC | 8 | 0 | 16 | 0 | 10 | 2 | 0 | 0 | 7 | 2 | 1 | 2 | 14 | 2 | 2 | 0 | 9
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 0 | 7
+IMPORTS | 1 | 0 | 9
+EQ | 12 |
+ LED<2>.D = LED<6> & LED<3> & alreadystoredcnt<0>
+ # LED<6> & LED<3> & !HZIN
+;Imported pterms FB1_10
+ # !LED<6> & LED<2> & alreadystoredcnt<0>
+ # !LED<6> & LED<2> & !HZIN
+ # !alreadystoredcnt<0> & HZIN & clkcounta<6>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ LED<2>.CLK = XSTALIN;
+ storecounta<9>.EXP = !LED<6> & LED<1> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 2 | 0 | alreadystoredcnt<0>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 51 | 2 | 1 | 0 | 16 | 0 | 10 | 0 | 13 | 0 | 14 | 0 | 5 | 0 | 7 | 0 | 8 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 11 | 2 | 13 | 2 | 12 | 2 | 5 | 1 | 17 | 3 | 0 | 3 | 17 | 3 | 14 | 3 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 3 | 16 | 2 | 4 | 2 | 3 | 1 | 16 | 1 | 15 | 1 | 0 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14 | 0 | 6 | 0 | 9 | 0 | 11 | 0 | 12 | 0 | 15 | 2 | 11 | 3 | 1 | 3 | 12 | 3 | 15
+INPUTS | 9 | alreadystoredcnt<0> | HZIN | LED<6> | storecounta<3> | LED<7> | resetclk<0> | XSTALIN | uartskip<0> | waitnow<0>.EXP
+INPUTMC | 7 | 2 | 0 | 0 | 16 | 2 | 17 | 2 | 1 | 2 | 14 | 2 | 2 | 2 | 1
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 17
+IMPORTS | 1 | 2 | 1
+EQ | 9 |
+ !alreadystoredcnt<0>.D = !alreadystoredcnt<0> & !HZIN
+;Imported pterms FB3_2
+ # LED<7> & !LED<6> & !resetclk<0> & uartskip<0> &
+ !HZIN;
+ alreadystoredcnt<0>.CLK = XSTALIN;
+ alreadystoredcnt<0>.EXP = !LED<6> & alreadystoredcnt<0> & storecounta<3>
+ # !LED<6> & storecounta<3> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 2 | 14 | resetclk<0>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 42 | 2 | 1 | 0 | 16 | 0 | 9 | 0 | 12 | 0 | 11 | 1 | 14 | 0 | 6 | 1 | 7 | 0 | 15 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 12 | 2 | 13 | 2 | 12 | 2 | 5 | 1 | 0 | 2 | 17 | 3 | 11 | 3 | 14 | 3 | 13 | 0 | 8 | 2 | 0 | 2 | 14 | 3 | 15 | 2 | 4 | 2 | 3 | 1 | 16 | 1 | 15 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 3 | 0 | 3 | 1 | 2 | 15
+INPUTS | 8 | alreadystoredcnt<0> | HZIN | XSTALIN | LED<6> | storecounta<5> | LED<7> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 2 | 0 | 0 | 16 | 2 | 15 | 2 | 1 | 2 | 14 | 2 | 2
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 15
+EQ | 6 |
+ resetclk<0>.D = !alreadystoredcnt<0> & HZIN;
+ resetclk<0>.CLK = XSTALIN;
+ resetclk<0>.EXP = !LED<6> & alreadystoredcnt<0> & storecounta<5>
+ # !LED<6> & storecounta<5> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 2 | 2 | uartskip<0>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 27 | 2 | 1 | 0 | 16 | 0 | 9 | 0 | 12 | 0 | 11 | 2 | 3 | 0 | 6 | 3 | 15 | 0 | 15 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 11 | 2 | 12 | 2 | 11 | 2 | 5 | 1 | 0 | 2 | 17 | 3 | 1 | 3 | 13 | 3 | 12 | 0 | 8 | 2 | 0 | 2 | 14 | 3 | 0
+INPUTS | 7 | LED<7> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | LED<6> | HZIN | XSTALIN
+INPUTMC | 5 | 2 | 1 | 2 | 0 | 2 | 14 | 2 | 2 | 0 | 16
+INPUTP | 2 | 65 | 63
+EQ | 5 |
+ uartskip<0>.T = !LED<7> & alreadystoredcnt<0> & !resetclk<0> &
+ !uartskip<0>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ uartskip<0>.CLK = XSTALIN;
+
+MACROCELL | 2 | 9 | uartctr<0>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 8 | 2 | 1 | 0 | 16 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5 | 2 | 10
+INPUTS | 15 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | HZIN | XSTALIN | clkcounta<0> | clkcounta<1> | uartctr<1>.EXP
+INPUTMC | 13 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5 | 2 | 3 | 2 | 11 | 2 | 8
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 10
+IMPORTS | 1 | 2 | 8
+EQ | 13 |
+ uartctr<0>.T = !LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0>
+ # LED<6> & !alreadystoredcnt<0> & !resetclk<0> &
+ uartctr<0> & uartctr<1> & uartctr<2> & uartctr<3> &
+ uartctr<4> & !HZIN
+;Imported pterms FB3_9
+ # LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>;
+ uartctr<0>.CLK = XSTALIN;
+ uartctr<0>.EXP = !resetclk<0> & clkcounta<0> & clkcounta<1>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1>
+
+MACROCELL | 2 | 8 | uartctr<1>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 7 | 2 | 1 | 0 | 16 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTS | 12 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | HZIN | XSTALIN
+INPUTMC | 10 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 9
+EQ | 12 |
+ uartctr<1>.T = !LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & uartctr<0>
+ # LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+ # LED<6> & !alreadystoredcnt<0> & !resetclk<0> &
+ uartctr<0> & uartctr<1> & uartctr<2> & uartctr<3> &
+ uartctr<4> & !HZIN;
+ uartctr<1>.CLK = XSTALIN;
+ uartctr<1>.EXP = LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+
+MACROCELL | 2 | 7 | uartctr<2>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 7 | 2 | 1 | 0 | 16 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTS | 12 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | HZIN | XSTALIN
+INPUTMC | 10 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTP | 2 | 65 | 63
+EQ | 9 |
+ uartctr<2>.T = !LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & uartctr<0> & uartctr<1>
+ # LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+ # LED<6> & !alreadystoredcnt<0> & !resetclk<0> &
+ uartctr<0> & uartctr<1> & uartctr<2> & uartctr<3> &
+ uartctr<4> & !HZIN;
+ uartctr<2>.CLK = XSTALIN;
+
+MACROCELL | 2 | 6 | uartctr<3>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 7 | 2 | 1 | 0 | 16 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTS | 12 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | HZIN | XSTALIN
+INPUTMC | 10 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTP | 2 | 65 | 63
+EQ | 10 |
+ uartctr<3>.T = !LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & uartctr<0> & uartctr<1> &
+ uartctr<2>
+ # LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+ # LED<6> & !alreadystoredcnt<0> & !resetclk<0> &
+ uartctr<0> & uartctr<1> & uartctr<2> & uartctr<3> &
+ uartctr<4> & !HZIN;
+ uartctr<3>.CLK = XSTALIN;
+
+MACROCELL | 3 | 12 | storecounta<18>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 3 | 12 | 3 | 13 | 3 | 11
+INPUTS | 10 | LED<6> | resetclk<0> | storecounta<18> | alreadystoredcnt<0> | storecounta<17> | HZIN | LED<7> | XSTALIN | uartskip<0> | EXP14_.EXP
+INPUTMC | 8 | 0 | 16 | 2 | 14 | 3 | 12 | 2 | 0 | 3 | 13 | 2 | 1 | 2 | 2 | 3 | 11
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 3 | 13
+IMPORTS | 1 | 3 | 11
+EQ | 12 |
+ storecounta<18>.D = LED<6> & !resetclk<0>
+ # !resetclk<0> & storecounta<18>
+;Imported pterms FB4_12
+ # LED<6> & !alreadystoredcnt<0> & HZIN
+ # !alreadystoredcnt<0> & storecounta<18> & HZIN
+ # LED<7> & alreadystoredcnt<0> & !resetclk<0> &
+ uartskip<0> & !HZIN;
+ storecounta<18>.CLK = XSTALIN;
+ storecounta<18>.EXP = !LED<6> & !alreadystoredcnt<0> & storecounta<17> &
+ HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 2 | 13 | storecounta<1>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 2 | 13 | 2 | 4
+INPUTS | 8 | LED<6> | resetclk<0> | storecounta<2> | storecounta<1> | alreadystoredcnt<0> | HZIN | storecounta<2>.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 2 | 14 | 2 | 12 | 2 | 13 | 2 | 0 | 2 | 12
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 2 | 12
+EQ | 10 |
+ storecounta<1>.D = LED<6> & !resetclk<0> & storecounta<2>
+ # !LED<6> & !resetclk<0> & storecounta<1>
+ # LED<6> & !alreadystoredcnt<0> & storecounta<2> &
+ HZIN
+ # !LED<6> & !alreadystoredcnt<0> & storecounta<1> &
+ HZIN
+;Imported pterms FB3_13
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<1>.CLK = XSTALIN;
+
+MACROCELL | 2 | 12 | storecounta<2>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 2 | 13 | 2 | 11
+INPUTS | 9 | alreadystoredcnt<0> | resetclk<0> | HZIN | LED<6> | storecounta<3> | LED<7> | uartskip<0> | clkcounta<1>.EXP | XSTALIN
+INPUTMC | 7 | 2 | 0 | 2 | 14 | 0 | 16 | 2 | 17 | 2 | 1 | 2 | 2 | 2 | 11
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 13
+IMPORTS | 1 | 2 | 11
+EQ | 10 |
+ storecounta<2>.D = LED<6> & storecounta<3>
+ # alreadystoredcnt<0> & resetclk<0>
+ # resetclk<0> & !HZIN
+;Imported pterms FB3_12
+ # !LED<6> & storecounta<2>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ uartskip<0> & !HZIN;
+ storecounta<2>.CLK = XSTALIN;
+ storecounta<2>.EXP = LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 2 | 5 | uartctr<4>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 7 | 2 | 1 | 0 | 16 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5
+INPUTS | 12 | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartctr<0> | uartctr<1> | uartctr<2> | uartctr<3> | uartctr<4> | HZIN | LED<7> | uartskip<0> | XSTALIN
+INPUTMC | 10 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 2 | 5 | 2 | 1 | 2 | 2
+INPUTP | 2 | 65 | 63
+EQ | 10 |
+ uartctr<4>.T = LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartctr<0> & uartctr<1> & uartctr<2> &
+ uartctr<3> & uartctr<4>
+ # !LED<7> & LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & uartctr<0> & uartctr<1> &
+ uartctr<2> & uartctr<3>
+ # LED<6> & !alreadystoredcnt<0> & !resetclk<0> &
+ uartctr<0> & uartctr<1> & uartctr<2> & uartctr<3> &
+ uartctr<4> & !HZIN;
+ uartctr<4>.CLK = XSTALIN;
+
+MACROCELL | 1 | 17 | storecounta<13>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 0 | 14 | 1 | 17 | 1 | 0
+INPUTS | 8 | LED<6> | alreadystoredcnt<0> | storecounta<14> | HZIN | clkcounta<10> | storecounta<13> | EXP12_.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 2 | 0 | 3 | 0 | 1 | 16 | 1 | 17 | 1 | 0
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 1 | 0
+EQ | 9 |
+ storecounta<13>.D = LED<6> & alreadystoredcnt<0> & storecounta<14>
+ # LED<6> & storecounta<14> & !HZIN
+ # !LED<6> & alreadystoredcnt<0> & storecounta<13>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<10>
+;Imported pterms FB2_1
+ # !LED<6> & storecounta<13> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<13>.CLK = XSTALIN;
+
+MACROCELL | 3 | 0 | storecounta<14>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 1 | 17 | 3 | 1 | 3 | 17
+INPUTS | 9 | LED<6> | alreadystoredcnt<0> | storecounta<15> | HZIN | LED<7> | resetclk<0> | uartskip<0> | EXP13_.EXP | XSTALIN
+INPUTMC | 7 | 0 | 16 | 2 | 0 | 3 | 17 | 2 | 1 | 2 | 14 | 2 | 2 | 3 | 1
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 3 | 17
+IMPORTS | 1 | 3 | 1
+EQ | 12 |
+ storecounta<14>.D = LED<6> & alreadystoredcnt<0> & storecounta<15>
+ # LED<6> & storecounta<15> & !HZIN
+;Imported pterms FB4_2
+ # !LED<6> & alreadystoredcnt<0> & storecounta<14>
+ # !LED<6> & storecounta<14> & !HZIN
+ # !alreadystoredcnt<0> & HZIN & clkcounta<11>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<14>.CLK = XSTALIN;
+ storecounta<14>.EXP = !LED<6> & storecounta<15> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 3 | 17 | storecounta<15>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 3 | 0 | 3 | 17
+INPUTS | 8 | LED<6> | alreadystoredcnt<0> | storecounta<16> | HZIN | clkcounta<12> | storecounta<15> | storecounta<14>.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 2 | 0 | 3 | 14 | 1 | 14 | 3 | 17 | 3 | 0
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 3 | 0
+EQ | 9 |
+ storecounta<15>.D = LED<6> & alreadystoredcnt<0> & storecounta<16>
+ # LED<6> & storecounta<16> & !HZIN
+ # !LED<6> & alreadystoredcnt<0> & storecounta<15>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<12>
+;Imported pterms FB4_1
+ # !LED<6> & storecounta<15> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<15>.CLK = XSTALIN;
+
+MACROCELL | 3 | 14 | storecounta<16>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 3 | 17 | 3 | 14
+INPUTS | 8 | alreadystoredcnt<0> | resetclk<0> | HZIN | LED<6> | storecounta<17> | storecounta<16> | storecounta<17>.EXP | XSTALIN
+INPUTMC | 6 | 2 | 0 | 2 | 14 | 0 | 16 | 3 | 13 | 3 | 14 | 3 | 13
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 3 | 13
+EQ | 8 |
+ storecounta<16>.D = LED<6> & storecounta<17>
+ # !LED<6> & storecounta<16>
+ # alreadystoredcnt<0> & resetclk<0>
+ # resetclk<0> & !HZIN
+;Imported pterms FB4_14
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ uartskip<0> & !HZIN;
+ storecounta<16>.CLK = XSTALIN;
+
+MACROCELL | 3 | 13 | storecounta<17>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 3 | 14 | 3 | 13 | 3 | 12
+INPUTS | 10 | LED<6> | resetclk<0> | storecounta<18> | storecounta<17> | alreadystoredcnt<0> | HZIN | LED<7> | uartskip<0> | XSTALIN | storecounta<18>.EXP
+INPUTMC | 8 | 0 | 16 | 2 | 14 | 3 | 12 | 3 | 13 | 2 | 0 | 2 | 1 | 2 | 2 | 3 | 12
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 3 | 14
+IMPORTS | 1 | 3 | 12
+EQ | 12 |
+ storecounta<17>.D = LED<6> & !resetclk<0> & storecounta<18>
+ # !LED<6> & !resetclk<0> & storecounta<17>
+ # LED<6> & !alreadystoredcnt<0> & storecounta<18> &
+ HZIN
+;Imported pterms FB4_13
+ # !LED<6> & !alreadystoredcnt<0> & storecounta<17> &
+ HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<17>.CLK = XSTALIN;
+ storecounta<17>.EXP = LED<7> & !LED<6> & alreadystoredcnt<0> &
+ uartskip<0> & !HZIN
+
+MACROCELL | 2 | 17 | storecounta<3>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 2 | 12 | 2 | 0 | 2 | 16
+INPUTS | 10 | LED<6> | alreadystoredcnt<0> | storecounta<4> | HZIN | clkcounta<0> | LED<7> | resetclk<0> | uartskip<0> | alreadystoredcnt<0>.EXP | XSTALIN
+INPUTMC | 8 | 0 | 16 | 2 | 0 | 2 | 16 | 2 | 3 | 2 | 1 | 2 | 14 | 2 | 2 | 2 | 0
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 16
+IMPORTS | 1 | 2 | 0
+EQ | 11 |
+ storecounta<3>.D = LED<6> & alreadystoredcnt<0> & storecounta<4>
+ # LED<6> & storecounta<4> & !HZIN
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0>
+;Imported pterms FB3_1
+ # !LED<6> & alreadystoredcnt<0> & storecounta<3>
+ # !LED<6> & storecounta<3> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<3>.CLK = XSTALIN;
+ storecounta<3>.EXP = LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 2 | 16 | storecounta<4>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 2 | 17 | 2 | 16 | 2 | 15
+INPUTS | 9 | LED<6> | alreadystoredcnt<0> | storecounta<5> | HZIN | clkcounta<1> | storecounta<4> | storecounta<5>.EXP | storecounta<3>.EXP | XSTALIN
+INPUTMC | 7 | 0 | 16 | 2 | 0 | 2 | 15 | 2 | 11 | 2 | 16 | 2 | 15 | 2 | 17
+INPUTP | 2 | 65 | 63
+IMPORTS | 2 | 2 | 15 | 2 | 17
+EQ | 10 |
+ storecounta<4>.D = LED<6> & alreadystoredcnt<0> & storecounta<5>
+ # LED<6> & storecounta<5> & !HZIN
+ # !LED<6> & alreadystoredcnt<0> & storecounta<4>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<1>
+;Imported pterms FB3_16
+ # !LED<6> & storecounta<4> & !HZIN
+;Imported pterms FB3_18
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<4>.CLK = XSTALIN;
+
+MACROCELL | 2 | 15 | storecounta<5>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 2 | 16 | 2 | 14
+INPUTS | 8 | LED<6> | alreadystoredcnt<0> | storecounta<6> | HZIN | clkcounta<2> | storecounta<4> | resetclk<0>.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 2 | 0 | 3 | 16 | 2 | 10 | 2 | 16 | 2 | 14
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 16
+IMPORTS | 1 | 2 | 14
+EQ | 10 |
+ storecounta<5>.D = LED<6> & alreadystoredcnt<0> & storecounta<6>
+ # LED<6> & storecounta<6> & !HZIN
+ # !alreadystoredcnt<0> & HZIN & clkcounta<2>
+;Imported pterms FB3_15
+ # !LED<6> & alreadystoredcnt<0> & storecounta<5>
+ # !LED<6> & storecounta<5> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<5>.CLK = XSTALIN;
+ storecounta<5>.EXP = !LED<6> & storecounta<4> & !HZIN
+
+MACROCELL | 3 | 16 | storecounta<6>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 2 | 15 | 3 | 16 | 3 | 15
+INPUTS | 8 | LED<6> | LED<0> | alreadystoredcnt<0> | HZIN | clkcounta<3> | storecounta<6> | EXP15_.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 0 | 5 | 2 | 0 | 1 | 13 | 3 | 16 | 3 | 15
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 3 | 15
+EQ | 9 |
+ storecounta<6>.D = LED<6> & LED<0> & alreadystoredcnt<0>
+ # LED<6> & LED<0> & !HZIN
+ # !LED<6> & alreadystoredcnt<0> & storecounta<6>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<3>
+;Imported pterms FB4_16
+ # !LED<6> & storecounta<6> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ storecounta<6>.CLK = XSTALIN;
+
+MACROCELL | 2 | 4 | storecounta<0>
+ATTRIBUTES | 8782626 | 0
+OUTPUTMC | 1 | 2 | 4
+INPUTS | 8 | LED<6> | resetclk<0> | storecounta<1> | TX | alreadystoredcnt<0> | HZIN | clkcounta<0>.EXP | XSTALIN
+INPUTMC | 6 | 0 | 16 | 2 | 14 | 2 | 13 | 2 | 4 | 2 | 0 | 2 | 3
+INPUTP | 2 | 65 | 63
+IMPORTS | 1 | 2 | 3
+EQ | 9 |
+ TX.D = LED<6> & !resetclk<0> & storecounta<1>
+ # !LED<6> & !resetclk<0> & TX
+ # LED<6> & !alreadystoredcnt<0> & storecounta<1> &
+ HZIN
+ # !LED<6> & !alreadystoredcnt<0> & HZIN & TX
+;Imported pterms FB3_4
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN;
+ TX.CLK = XSTALIN;
+
+MACROCELL | 2 | 3 | clkcounta<0>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 16 | 2 | 17 | 2 | 3 | 1 | 16 | 1 | 15 | 2 | 11 | 2 | 9 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14 | 2 | 10 | 2 | 4
+INPUTS | 8 | resetclk<0> | clkcounta<0> | alreadystoredcnt<0> | HZIN | XSTALIN | LED<7> | LED<6> | uartskip<0>
+INPUTMC | 6 | 2 | 14 | 2 | 3 | 2 | 0 | 2 | 1 | 0 | 16 | 2 | 2
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 4
+EQ | 5 |
+ clkcounta<0>.D = !resetclk<0> & !clkcounta<0>
+ # !alreadystoredcnt<0> & HZIN & !clkcounta<0>;
+ clkcounta<0>.CLK = XSTALIN;
+ clkcounta<0>.EXP = LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 1 | 16 | clkcounta<10>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 4 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14
+INPUTS | 15 | alreadystoredcnt<0> | resetclk<0> | clkcounta<10> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | clkcounta<6> | clkcounta<7> | clkcounta<8> | clkcounta<9> | XSTALIN
+INPUTMC | 13 | 2 | 0 | 2 | 14 | 1 | 16 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7
+INPUTP | 2 | 65 | 63
+EQ | 11 |
+ clkcounta<10>.T = alreadystoredcnt<0> & resetclk<0> &
+ clkcounta<10>
+ # resetclk<0> & !HZIN & clkcounta<10>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3> & clkcounta<4> & clkcounta<5> &
+ clkcounta<6> & clkcounta<7> & clkcounta<8> & clkcounta<9>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4> &
+ clkcounta<5> & clkcounta<6> & clkcounta<7> & clkcounta<8> &
+ clkcounta<9>;
+ clkcounta<10>.CLK = XSTALIN;
+
+MACROCELL | 1 | 15 | clkcounta<11>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 3 | 1 | 14 | 1 | 15 | 3 | 1
+INPUTS | 16 | alreadystoredcnt<0> | resetclk<0> | clkcounta<11> | HZIN | clkcounta<0> | clkcounta<10> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | clkcounta<6> | clkcounta<7> | clkcounta<8> | clkcounta<9> | XSTALIN
+INPUTMC | 14 | 2 | 0 | 2 | 14 | 1 | 15 | 2 | 3 | 1 | 16 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7
+INPUTP | 2 | 65 | 63
+EQ | 12 |
+ clkcounta<11>.T = alreadystoredcnt<0> & resetclk<0> &
+ clkcounta<11>
+ # resetclk<0> & !HZIN & clkcounta<11>
+ # !resetclk<0> & clkcounta<0> & clkcounta<10> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4> &
+ clkcounta<5> & clkcounta<6> & clkcounta<7> & clkcounta<8> &
+ clkcounta<9>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<10> & clkcounta<1> & clkcounta<2> & clkcounta<3> &
+ clkcounta<4> & clkcounta<5> & clkcounta<6> & clkcounta<7> &
+ clkcounta<8> & clkcounta<9>;
+ clkcounta<11>.CLK = XSTALIN;
+
+MACROCELL | 2 | 11 | clkcounta<1>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 15 | 2 | 16 | 1 | 16 | 1 | 15 | 2 | 11 | 2 | 9 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14 | 2 | 10 | 2 | 12
+INPUTS | 11 | resetclk<0> | clkcounta<0> | clkcounta<1> | LED<6> | storecounta<2> | XSTALIN | LED<7> | alreadystoredcnt<0> | uartskip<0> | HZIN | clkcounta<2>.EXP
+INPUTMC | 9 | 2 | 14 | 2 | 3 | 2 | 11 | 0 | 16 | 2 | 12 | 2 | 1 | 2 | 0 | 2 | 2 | 2 | 10
+INPUTP | 2 | 63 | 65
+EXPORTS | 1 | 2 | 12
+IMPORTS | 1 | 2 | 10
+EQ | 11 |
+ clkcounta<1>.D = !resetclk<0> & clkcounta<0> & !clkcounta<1>
+ # !resetclk<0> & !clkcounta<0> & clkcounta<1>
+;Imported pterms FB3_11
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ !clkcounta<1>
+ # !alreadystoredcnt<0> & HZIN & !clkcounta<0> &
+ clkcounta<1>;
+ clkcounta<1>.CLK = XSTALIN;
+ clkcounta<1>.EXP = !LED<6> & storecounta<2>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ uartskip<0> & !HZIN
+
+MACROCELL | 2 | 10 | clkcounta<2>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 13 | 2 | 15 | 1 | 16 | 1 | 15 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14 | 2 | 11
+INPUTS | 8 | alreadystoredcnt<0> | resetclk<0> | clkcounta<2> | HZIN | clkcounta<0> | clkcounta<1> | XSTALIN | uartctr<0>.EXP
+INPUTMC | 6 | 2 | 0 | 2 | 14 | 2 | 10 | 2 | 3 | 2 | 11 | 2 | 9
+INPUTP | 2 | 65 | 63
+EXPORTS | 1 | 2 | 11
+IMPORTS | 1 | 2 | 9
+EQ | 11 |
+ clkcounta<2>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<2>
+ # resetclk<0> & !HZIN & clkcounta<2>
+;Imported pterms FB3_10
+ # !resetclk<0> & clkcounta<0> & clkcounta<1>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1>;
+ clkcounta<2>.CLK = XSTALIN;
+ clkcounta<2>.EXP = !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ !clkcounta<1>
+ # !alreadystoredcnt<0> & HZIN & !clkcounta<0> &
+ clkcounta<1>
+
+MACROCELL | 1 | 13 | clkcounta<3>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 11 | 3 | 16 | 1 | 16 | 1 | 15 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14
+INPUTS | 8 | alreadystoredcnt<0> | resetclk<0> | clkcounta<3> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | XSTALIN
+INPUTMC | 6 | 2 | 0 | 2 | 14 | 1 | 13 | 2 | 3 | 2 | 11 | 2 | 10
+INPUTP | 2 | 65 | 63
+EQ | 7 |
+ clkcounta<3>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<3>
+ # resetclk<0> & !HZIN & clkcounta<3>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2>;
+ clkcounta<3>.CLK = XSTALIN;
+
+MACROCELL | 1 | 12 | clkcounta<4>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 10 | 0 | 5 | 1 | 16 | 1 | 15 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14
+INPUTS | 9 | alreadystoredcnt<0> | resetclk<0> | clkcounta<4> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | XSTALIN
+INPUTMC | 7 | 2 | 0 | 2 | 14 | 1 | 12 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13
+INPUTP | 2 | 65 | 63
+EQ | 7 |
+ clkcounta<4>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<4>
+ # resetclk<0> & !HZIN & clkcounta<4>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3>;
+ clkcounta<4>.CLK = XSTALIN;
+
+MACROCELL | 1 | 11 | clkcounta<5>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 9 | 0 | 7 | 1 | 16 | 1 | 15 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14
+INPUTS | 10 | alreadystoredcnt<0> | resetclk<0> | clkcounta<5> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | XSTALIN
+INPUTMC | 8 | 2 | 0 | 2 | 14 | 1 | 11 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12
+INPUTP | 2 | 65 | 63
+EQ | 7 |
+ clkcounta<5>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<5>
+ # resetclk<0> & !HZIN & clkcounta<5>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3> & clkcounta<4>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4>;
+ clkcounta<5>.CLK = XSTALIN;
+
+MACROCELL | 1 | 10 | clkcounta<6>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 8 | 1 | 14 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 0 | 9
+INPUTS | 11 | alreadystoredcnt<0> | resetclk<0> | clkcounta<6> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | XSTALIN
+INPUTMC | 9 | 2 | 0 | 2 | 14 | 1 | 10 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11
+INPUTP | 2 | 65 | 63
+EQ | 8 |
+ clkcounta<6>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<6>
+ # resetclk<0> & !HZIN & clkcounta<6>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3> & clkcounta<4> & clkcounta<5>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4> &
+ clkcounta<5>;
+ clkcounta<6>.CLK = XSTALIN;
+
+MACROCELL | 1 | 9 | clkcounta<7>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 7 | 0 | 10 | 1 | 16 | 1 | 15 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14
+INPUTS | 12 | alreadystoredcnt<0> | resetclk<0> | clkcounta<7> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | clkcounta<6> | XSTALIN
+INPUTMC | 10 | 2 | 0 | 2 | 14 | 1 | 9 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10
+INPUTP | 2 | 65 | 63
+EQ | 9 |
+ clkcounta<7>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<7>
+ # resetclk<0> & !HZIN & clkcounta<7>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3> & clkcounta<4> & clkcounta<5> &
+ clkcounta<6>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4> &
+ clkcounta<5> & clkcounta<6>;
+ clkcounta<7>.CLK = XSTALIN;
+
+MACROCELL | 1 | 8 | clkcounta<8>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 6 | 0 | 13 | 1 | 16 | 1 | 15 | 1 | 8 | 1 | 7 | 1 | 14
+INPUTS | 13 | alreadystoredcnt<0> | resetclk<0> | clkcounta<8> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | clkcounta<6> | clkcounta<7> | XSTALIN
+INPUTMC | 11 | 2 | 0 | 2 | 14 | 1 | 8 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9
+INPUTP | 2 | 65 | 63
+EQ | 9 |
+ clkcounta<8>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<8>
+ # resetclk<0> & !HZIN & clkcounta<8>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3> & clkcounta<4> & clkcounta<5> &
+ clkcounta<6> & clkcounta<7>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4> &
+ clkcounta<5> & clkcounta<6> & clkcounta<7>;
+ clkcounta<8>.CLK = XSTALIN;
+
+MACROCELL | 1 | 7 | clkcounta<9>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 5 | 0 | 14 | 1 | 16 | 1 | 15 | 1 | 7 | 1 | 14
+INPUTS | 14 | alreadystoredcnt<0> | resetclk<0> | clkcounta<9> | HZIN | clkcounta<0> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | clkcounta<6> | clkcounta<7> | clkcounta<8> | XSTALIN
+INPUTMC | 12 | 2 | 0 | 2 | 14 | 1 | 7 | 2 | 3 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8
+INPUTP | 2 | 65 | 63
+EQ | 9 |
+ clkcounta<9>.T = alreadystoredcnt<0> & resetclk<0> & clkcounta<9>
+ # resetclk<0> & !HZIN & clkcounta<9>
+ # !resetclk<0> & clkcounta<0> & clkcounta<1> &
+ clkcounta<2> & clkcounta<3> & clkcounta<4> & clkcounta<5> &
+ clkcounta<6> & clkcounta<7> & clkcounta<8>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<1> & clkcounta<2> & clkcounta<3> & clkcounta<4> &
+ clkcounta<5> & clkcounta<6> & clkcounta<7> & clkcounta<8>;
+ clkcounta<9>.CLK = XSTALIN;
+
+MACROCELL | 1 | 14 | clkcounta<12>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 2 | 3 | 17 | 1 | 14
+INPUTS | 17 | alreadystoredcnt<0> | resetclk<0> | clkcounta<12> | HZIN | clkcounta<0> | clkcounta<10> | clkcounta<11> | clkcounta<1> | clkcounta<2> | clkcounta<3> | clkcounta<4> | clkcounta<5> | clkcounta<6> | clkcounta<7> | clkcounta<8> | clkcounta<9> | XSTALIN
+INPUTMC | 15 | 2 | 0 | 2 | 14 | 1 | 14 | 2 | 3 | 1 | 16 | 1 | 15 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7
+INPUTP | 2 | 65 | 63
+EQ | 12 |
+ clkcounta<12>.T = alreadystoredcnt<0> & resetclk<0> &
+ clkcounta<12>
+ # resetclk<0> & !HZIN & clkcounta<12>
+ # !resetclk<0> & clkcounta<0> & clkcounta<10> &
+ clkcounta<11> & clkcounta<1> & clkcounta<2> & clkcounta<3> &
+ clkcounta<4> & clkcounta<5> & clkcounta<6> & clkcounta<7> &
+ clkcounta<8> & clkcounta<9>
+ # !alreadystoredcnt<0> & HZIN & clkcounta<0> &
+ clkcounta<10> & clkcounta<11> & clkcounta<1> & clkcounta<2> &
+ clkcounta<3> & clkcounta<4> & clkcounta<5> & clkcounta<6> &
+ clkcounta<7> & clkcounta<8> & clkcounta<9>;
+ clkcounta<12>.CLK = XSTALIN;
+
+MACROCELL | 0 | 4 | EXP6_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 5
+INPUTS | 3 | LED<6> | LED<0> | HZIN
+INPUTMC | 2 | 0 | 16 | 0 | 5
+INPUTP | 1 | 65
+EXPORTS | 1 | 0 | 5
+EQ | 1 |
+ EXP6_.EXP = !LED<6> & LED<0> & !HZIN
+
+MACROCELL | 0 | 6 | EXP7_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 5
+INPUTS | 6 | LED<7> | LED<6> | alreadystoredcnt<0> | resetclk<0> | uartskip<0> | HZIN
+INPUTMC | 5 | 2 | 1 | 0 | 16 | 2 | 0 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 0 | 5
+EQ | 2 |
+ EXP7_.EXP = LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 0 | 9 | EXP8_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 8
+INPUTS | 8 | LED<6> | LED<2> | alreadystoredcnt<0> | HZIN | clkcounta<6> | LED<7> | resetclk<0> | uartskip<0>
+INPUTMC | 7 | 0 | 16 | 0 | 8 | 2 | 0 | 1 | 10 | 2 | 1 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 0 | 8
+EQ | 5 |
+ EXP8_.EXP = !LED<6> & LED<2> & alreadystoredcnt<0>
+ # !LED<6> & LED<2> & !HZIN
+ # !alreadystoredcnt<0> & HZIN & clkcounta<6>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 0 | 11 | EXP9_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 10
+INPUTS | 7 | LED<6> | LED<3> | HZIN | LED<7> | alreadystoredcnt<0> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 0 | 16 | 0 | 10 | 2 | 1 | 2 | 0 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 0 | 10
+EQ | 3 |
+ EXP9_.EXP = !LED<6> & LED<3> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 0 | 12 | EXP10_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 13
+INPUTS | 7 | LED<6> | LED<4> | HZIN | LED<7> | alreadystoredcnt<0> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 0 | 16 | 0 | 13 | 2 | 1 | 2 | 0 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 0 | 13
+EQ | 3 |
+ EXP10_.EXP = !LED<6> & LED<4> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 0 | 15 | EXP11_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 14
+INPUTS | 7 | LED<6> | LED<5> | HZIN | LED<7> | alreadystoredcnt<0> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 0 | 16 | 0 | 14 | 2 | 1 | 2 | 0 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 0 | 14
+EQ | 3 |
+ EXP11_.EXP = !LED<6> & LED<5> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 1 | 0 | EXP12_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 1 | 17
+INPUTS | 7 | LED<6> | storecounta<13> | HZIN | LED<7> | alreadystoredcnt<0> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 0 | 16 | 1 | 17 | 2 | 1 | 2 | 0 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 1 | 17
+EQ | 3 |
+ EXP12_.EXP = !LED<6> & storecounta<13> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 3 | 1 | EXP13_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 3 | 0
+INPUTS | 8 | LED<6> | alreadystoredcnt<0> | storecounta<14> | HZIN | clkcounta<11> | LED<7> | resetclk<0> | uartskip<0>
+INPUTMC | 7 | 0 | 16 | 2 | 0 | 3 | 0 | 1 | 15 | 2 | 1 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 3 | 0
+EQ | 5 |
+ EXP13_.EXP = !LED<6> & alreadystoredcnt<0> & storecounta<14>
+ # !LED<6> & storecounta<14> & !HZIN
+ # !alreadystoredcnt<0> & HZIN & clkcounta<11>
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+MACROCELL | 3 | 11 | EXP14_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 3 | 12
+INPUTS | 7 | LED<6> | alreadystoredcnt<0> | HZIN | storecounta<18> | LED<7> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 0 | 16 | 2 | 0 | 3 | 12 | 2 | 1 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 3 | 12
+EQ | 4 |
+ EXP14_.EXP = LED<6> & !alreadystoredcnt<0> & HZIN
+ # !alreadystoredcnt<0> & storecounta<18> & HZIN
+ # LED<7> & alreadystoredcnt<0> & !resetclk<0> &
+ uartskip<0> & !HZIN
+
+MACROCELL | 3 | 15 | EXP15_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 3 | 16
+INPUTS | 7 | LED<6> | storecounta<6> | HZIN | LED<7> | alreadystoredcnt<0> | resetclk<0> | uartskip<0>
+INPUTMC | 6 | 0 | 16 | 3 | 16 | 2 | 1 | 2 | 0 | 2 | 14 | 2 | 2
+INPUTP | 1 | 65
+EXPORTS | 1 | 3 | 16
+EQ | 3 |
+ EXP15_.EXP = !LED<6> & storecounta<6> & !HZIN
+ # LED<7> & !LED<6> & alreadystoredcnt<0> &
+ !resetclk<0> & uartskip<0> & !HZIN
+
+PIN | XSTALIN | 64 | 0 | N/A | 63 | 42 | 2 | 1 | 0 | 16 | 0 | 10 | 0 | 13 | 0 | 14 | 0 | 5 | 0 | 7 | 0 | 8 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 12 | 2 | 13 | 2 | 12 | 2 | 5 | 1 | 17 | 3 | 0 | 3 | 17 | 3 | 14 | 3 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 3 | 16 | 2 | 4 | 2 | 3 | 1 | 16 | 1 | 15 | 2 | 11 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14
+PIN | HZIN | 64 | 0 | N/A | 65 | 52 | 2 | 1 | 0 | 16 | 0 | 10 | 0 | 13 | 0 | 14 | 0 | 5 | 0 | 7 | 0 | 8 | 2 | 0 | 2 | 14 | 2 | 2 | 2 | 9 | 2 | 8 | 2 | 7 | 2 | 6 | 3 | 11 | 2 | 13 | 2 | 12 | 2 | 5 | 1 | 17 | 3 | 0 | 3 | 17 | 3 | 14 | 3 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 3 | 16 | 2 | 4 | 2 | 3 | 1 | 16 | 1 | 15 | 1 | 0 | 2 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 14 | 0 | 4 | 0 | 6 | 0 | 9 | 0 | 11 | 0 | 12 | 0 | 15 | 2 | 11 | 3 | 1 | 3 | 12 | 3 | 15
+PIN | LED<7> | 536871040 | 0 | N/A | 29
+PIN | LED<6> | 536871040 | 0 | N/A | 27
+PIN | LED<3> | 536871040 | 0 | N/A | 21
+PIN | LED<4> | 536871040 | 0 | N/A | 24
+PIN | LED<5> | 536871040 | 0 | N/A | 26
+PIN | LED<0> | 536871040 | 0 | N/A | 13
+PIN | LED<1> | 536871040 | 0 | N/A | 15
+PIN | LED<2> | 536871040 | 0 | N/A | 20
+PIN | TX | 536871040 | 0 | N/A | 31
diff --git a/60hz_Divider/code/xilinx/cpld_countertest10/counta.nga b/60hz_Divider/code/xilinx/cpld_countertest10/counta.nga
new file mode 100644
index 0000000..ec41270
--- /dev/null
+++ b/60hz_Divider/code/xilinx/cpld_countertest10/counta.nga
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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