library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

entity counter is
    port (
        CLK_IN: in std_logic;
        RLED: out std_logic_vector(3 downto 0)
    );
end counter ; 

architecture behav of counter is

    signal pres_count, next_count: std_logic_vector(3 downto 0);

begin

    RLED <= pres_count;

    sync_count: process(CLK_IN)
    begin
        if(rising_edge(CLK_IN)) then
                pres_count <= pres_count + 1;
        end if;
    end process sync_count;

end architecture;