Environment Settings | ||
Environment Variable | xst | ngdbuild |
LD_LIBRARY_PATH | /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin | /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin |
PATH | /opt/Xilinx/14.7/ISE_DS/ISE//bin/lin: /home/dev/bin: /usr/local/bin: /usr/bin: /bin: /usr/local/games: /usr/games |
/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin: /home/dev/bin: /usr/local/bin: /usr/bin: /bin: /usr/local/games: /usr/games |
XILINX | /opt/Xilinx/14.7/ISE_DS/ISE/ | /opt/Xilinx/14.7/ISE_DS/ISE/ |
Synthesis Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-ifn | counta.prj | ||
-ifmt | mixed | MIXED | |
-ofn | counta | ||
-ofmt | NGC | NGC | |
-p | xc9500xl | ||
-top | counta | ||
-opt_mode | Optimization Goal | Speed | SPEED |
-opt_level | Optimization Effort | 1 | 1 |
-iuc | Use synthesis Constraints File | NO | NO |
-keep_hierarchy | Keep Hierarchy | Yes | YES |
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized |
-rtlview | Generate RTL Schematic | Yes | NO |
-bus_delimiter | Bus Delimiter | <> | <> |
-verilog2001 | Verilog 2001 | YES | YES |
-fsm_extract | YES | YES | |
-fsm_encoding | Auto | AUTO | |
-safe_implementation | No | NO | |
-resource_sharing | YES | YES | |
-iobuf | YES | YES | |
-equivalent_register_removal | YES | YES |
Translation Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-intstyle | ise | None | |
-dd | _ngo | None | |
-p | xc9572xl-VQ44-5 | None | |
-uc | constraints.ucf | None |
Operating System Information | ||
Operating System Information | xst | ngdbuild |
CPU Architecture/Speed | Intel(R) Core(TM) Duo CPU T2400 @ 1.83GHz/1333.000 MHz | Intel(R) Core(TM) Duo CPU T2400 @ 1.83GHz/1333.000 MHz |
Host | fpgamach | fpgamach |
OS Name | Devuan | Devuan |
OS Release | Devuan GNU/Linux ascii | Devuan GNU/Linux ascii |