| Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LED<4> | 7 | 10 | FB1 | MC14 | STD | FAST | 1 | I/O/GCK3 | O | RESET | |||
| LED<5> | 7 | 10 | FB1 | MC15 | STD | FAST | 2 | I/O | O | RESET | |||
| LED<6> | 5 | 12 | FB1 | MC17 | STD | FAST | 3 | I/O | O | RESET | |||
| LED<7> | 4 | 12 | FB3 | MC2 | STD | FAST | 5 | I/O | O | RESET | |||
| TX | 6 | 9 | FB3 | MC5 | STD | FAST | 6 | I/O | O | RESET | |||
| uartctr<2> | 4 | 12 | FB3 | MC8 | STD | 7 | I/O | (b) | RESET | ||||
| uartctr<1> | 4 | 12 | FB3 | MC9 | STD | 8 | I/O | (b) | RESET | ||||
| clkcounta<2> | 5 | 7 | FB3 | MC11 | STD | 12 | I/O | (b) | RESET | ||||
| storecounta<1> | 6 | 9 | FB3 | MC14 | STD | 13 | I/O | (b) | RESET | ||||
| resetclk<0> | 2 | 3 | FB3 | MC15 | STD | 14 | I/O | (b) | RESET | ||||
| storecounta<4> | 7 | 10 | FB3 | MC17 | STD | 16 | I/O | (b) | RESET | ||||
| storecounta<5> | 7 | 10 | FB3 | MC16 | STD | 18 | I/O | (b) | RESET | ||||
| storecounta<17> | 6 | 9 | FB4 | MC14 | STD | 23 | I/O | (b) | RESET | ||||
| storecounta<16> | 6 | 9 | FB4 | MC15 | STD | 27 | I/O | (b) | RESET | ||||
| storecounta<6> | 7 | 10 | FB4 | MC17 | STD | 28 | I/O | (b) | RESET | ||||
| clkcounta<9> | 5 | 14 | FB2 | MC8 | STD | 32 | I/O | (b) | RESET | ||||
| clkcounta<8> | 5 | 13 | FB2 | MC9 | STD | 33 | I/O/GSR | (b) | RESET | ||||
| clkcounta<6> | 5 | 11 | FB2 | MC11 | STD | 34 | I/O/GTS2 | (b) | RESET | ||||
| clkcounta<3> | 5 | 8 | FB2 | MC14 | STD | 36 | I/O/GTS1 | (b) | RESET | ||||
| clkcounta<12> | 5 | 17 | FB2 | MC15 | STD | 37 | I/O | (b) | RESET | ||||
| clkcounta<10> | 5 | 15 | FB2 | MC17 | STD | 38 | I/O | (b) | RESET | ||||
| LED<0> | 7 | 10 | FB1 | MC6 | STD | FAST | 41 | I/O | O | RESET | |||
| LED<1> | 7 | 10 | FB1 | MC8 | STD | FAST | 42 | I/O | O | RESET | |||
| LED<2> | 7 | 10 | FB1 | MC9 | STD | FAST | 43 | I/O/GCK1 | O | RESET | |||
| LED<3> | 7 | 10 | FB1 | MC11 | STD | FAST | 44 | I/O/GCK2 | O | RESET | |||
| clkcounta<7> | 5 | 12 | FB2 | MC10 | STD | (b) | (b) | T | RESET | ||||
| clkcounta<5> | 5 | 10 | FB2 | MC12 | STD | (b) | (b) | T | RESET | ||||
| clkcounta<4> | 5 | 9 | FB2 | MC13 | STD | (b) | (b) | T | RESET | ||||
| clkcounta<11> | 5 | 16 | FB2 | MC16 | STD | (b) | (b) | T | RESET | ||||
| storecounta<13> | 7 | 10 | FB2 | MC18 | STD | (b) | (b) | D | RESET | ||||
| alreadystoredcnt<0> | 3 | 7 | FB3 | MC1 | STD | (b) | (b) | D | RESET | ||||
| uartskip<0> | 3 | 7 | FB3 | MC3 | STD | (b) | (b) | T | RESET | ||||
| clkcounta<0> | 3 | 5 | FB3 | MC4 | STD | (b) | (b) | D | RESET | ||||
| uartctr<4> | 4 | 12 | FB3 | MC6 | STD | (b) | (b) | T | RESET | ||||
| uartctr<3> | 4 | 12 | FB3 | MC7 | STD | (b) | (b) | T | RESET | ||||
| uartctr<0> | 4 | 12 | FB3 | MC10 | STD | (b) | (b) | T | RESET | ||||
| clkcounta<1> | 5 | 6 | FB3 | MC12 | STD | (b) | (b) | D | RESET | ||||
| storecounta<2> | 6 | 9 | FB3 | MC13 | STD | (b) | (b) | D | RESET | ||||
| storecounta<3> | 7 | 10 | FB3 | MC18 | STD | (b) | (b) | D | RESET | ||||
| storecounta<14> | 7 | 10 | FB4 | MC1 | STD | (b) | (b) | D | RESET | ||||
| storecounta<18> | 6 | 8 | FB4 | MC13 | STD | (b) | (b) | D | RESET | ||||
| storecounta<15> | 7 | 10 | FB4 | MC18 | STD | (b) | (b) | D | RESET |