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563 lines
32 KiB
563 lines
32 KiB
(kicad_pcb (version 20171130) (host pcbnew 5.0.0-rc2)
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(general
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(thickness 1.6)
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(drawings 68)
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(tracks 0)
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(zones 0)
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(modules 1)
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(nets 5)
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(page USLetter)
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(title_block
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(title "Project Title")
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)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(44 Edge.Cuts user)
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(46 B.CrtYd user hide)
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(47 F.CrtYd user hide)
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(48 B.Fab user hide)
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(49 F.Fab user hide)
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)
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(setup
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(trace_clearance 0.254)
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(via_size 0.6858)
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(via_drill 0.3302)
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(via_min_size 0.6858)
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(via_min_drill 0.3302)
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(user_via 0.6858 0.3302)
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(user_via 0.762 0.4064)
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(user_via 0.8636 0.508)
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(uvia_size 0.6858)
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(uvia_drill 0.3302)
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(uvias_allowed no)
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(pad_size 1.2 1.2)
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(solder_mask_min_width 0.1016)
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(mirror false)
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(drillshape 0)
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(scaleselection 1)
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(outputdirectory gerbers/))
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)
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(net 0 "")
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(net 1 /VOut+)
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(net 2 +5V)
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(net 3 GND)
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(net 4 /VSenseOUT)
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(net_class Default "This is the default net class."
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(module to_39:TO-39-4 (layer F.Cu) (tedit 5D1ADB97) (tstamp 5D11432E)
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(at 113.5 66)
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(descr TO-39-4)
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(tags TO-39-4)
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(net 2 +5V))
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(net 4 /VSenseOUT))
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(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-39-4.wrl
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(gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 28.6 161.5) (layer Dwgs.User)
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