(kicad_pcb (version 4) (host pcbnew 4.0.7-e2-6376~58~ubuntu16.04.1)
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(general
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(links 0)
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(no_connects 0)
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(area 104.572999 74.854999 178.510001 123.265001)
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(thickness 1.6)
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(drawings 1)
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(tracks 0)
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(zones 0)
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(modules 0)
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(nets 1)
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)
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(page USLetter)
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(title_block
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(title "Project Title")
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)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(44 Edge.Cuts user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.254)
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(user_trace_width 0.1524)
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(user_trace_width 0.254)
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(user_trace_width 0.3302)
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(user_trace_width 0.508)
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(user_trace_width 0.762)
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(user_trace_width 1.27)
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(trace_clearance 0.254)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.1524)
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(segment_width 0.1524)
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(edge_width 0.1524)
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(via_size 0.6858)
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(via_drill 0.3302)
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(via_min_size 0.6858)
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(via_min_drill 0.3302)
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(user_via 0.6858 0.3302)
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(user_via 0.762 0.4064)
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(user_via 0.8636 0.508)
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(uvia_size 0.6858)
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(uvia_drill 0.3302)
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(uvias_allowed no)
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(uvia_min_size 0)
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(uvia_min_drill 0)
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(pcb_text_width 0.1524)
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(pcb_text_size 1.016 1.016)
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(mod_edge_width 0.1524)
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(mod_text_size 1.016 1.016)
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(mod_text_width 0.1524)
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(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.0762)
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(solder_mask_min_width 0.1016)
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(pad_to_paste_clearance -0.0762)
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(aux_axis_origin 0 0)
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(visible_elements FFFEDF7D)
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(pcbplotparams
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(layerselection 0x310fc_80000001)
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(usegerberextensions true)
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(excludeedgelayer true)
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(linewidth 0.100000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 0)
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(scaleselection 1)
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(outputdirectory gerbers))
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)
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(net 0 "")
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(net_class Default "This is the default net class."
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(clearance 0.254)
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(trace_width 0.254)
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(via_dia 0.6858)
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(via_drill 0.3302)
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(uvia_dia 0.6858)
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(uvia_drill 0.3302)
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)
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(gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
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(effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
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)
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)
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