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- // File counter.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
- // vhd2vl settings:
- // * Verilog Module Declaration Style: 2001
-
- // vhd2vl is Free (libre) Software:
- // Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
- // http://www.ocean-logic.com
- // Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
- // Modifications (C) 2010 Shankar Giri
- // Modifications Copyright (C) 2002-2017 Larry Doolittle
- // http://doolittle.icarus.com/~larry/vhd2vl/
- // Modifications (C) 2017 Rodrigo A. Melo
- //
- // vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
- // Verilog for correctness, ideally with a formal verification tool.
- //
- // You are welcome to redistribute vhd2vl under certain conditions.
- // See the license (GPLv2) file included with the source for details.
-
- // The result of translation follows. Its copyright status should be
- // considered unchanged from the original VHDL.
-
- // no timescale needed
-
- module counter(
- input wire CLK_IN,
- output wire [3:0] RLED
- );
-
-
-
-
- reg [3:0] pres_count; wire [3:0] next_count;
-
- assign RLED = pres_count;
- always @(posedge CLK_IN) begin
- pres_count <= pres_count + 1;
- end
-
-
- endmodule
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