Electronics_Projects_2020/Attiny_Solar_Energy_Harvest/code/mplab/tests6_timer_6000hz.X/main.c

#include <xc.h>
#include <avr/io.h>
#include <util/delay.h>

#include <avr/interrupt.h>
//#include <avr/sleep.h>
//#include <util/atomic.h>
//#include <avr/wdt.h>



//tests5 tested and works (at ~950hz). unplug cable to programmer to see pin 4 active.
//however...
//tests6 DEADEND
//never worked right. giving up and using delay. 

//reference: https://www.avrfreaks.net/forum/sample-project-attiny10
//https://blog.podkalicki.com/attiny13-blinky-with-timer-compa/
//watchdog is too slow and inaccurate to get 6000Hz

ISR(TIM0_COMPA_vect)
{
        // Toggle PB2 Hi/Low depending on current state
        PINB = 1<<2;
        TIFR0 |= 1<<OCF0A; //clear flag (is this required here? documentation unclear)
        //PORTB ^= _BV(LED_PIN); // toggle LED pin
}


/*
  Delay in powerdown mode. Wake up by watchdog interrupt.
 * //NOTE: see earlier code, e.g. tests3 in attiny10  elec projects 2020
 */
/*
void delay_power_down_wdt(uint8_t wdto)
{
    wdt_reset();
    wdt_enable(wdto);
    WDTCSR |= (1<<WDIE);
    //so far (with 128Khz clk) this sleep will be about 30-40 seconds.
    
    //(however, I'll add the below to)
    //adjust sleep speed here:
    
    // 0110 is 1hz at 128KHz
    //WDTCSR |= (0<< WDP3);
    //WDTCSR |= (1<< WDP2);
    //WDTCSR |= (1<< WDP1);
    //WDTCSR |= (0<< WDP0);
    
    set_sleep_mode(SLEEP_MODE_PWR_DOWN);
    sleep_enable();
    // Make sure interrups are enabled and the I flag is restored
    NONATOMIC_BLOCK(NONATOMIC_RESTORESTATE)
    {
	sleep_cpu();
	wdt_disable();
    }
    sleep_disable();
}
*/

int main(void)
{
    
    
    
    OCR0A = 0;
    TCNT0 = 0; 
    TCCR0A = 0; 
    TCCR0B = 0;
    
    TCCR0A |= _BV(WGM01); // set timer counter mode to CTC
   // TCCR0B |= _BV(CS02)|_BV(CS00); // set prescaler to 1024 (CLK=1200000Hz/1024/256=4.57Hz, 0.22s)
    TCCR0B |=  _BV(CS00); // set prescaler to 1 (CLK=1MHz/1)
    //OCR0A is 16 bits. in ASM it must be loaded separately.
    //in C, it can be loaded > 256? (test)
    
    //520 about  950hz, 25us wide pulse
    //OCR0A = 520; // with one timer, ever 166.667hz we want to count once (3000hz)
    
    //OCR0A = 1; //475hz
    
    //this goes to 475hz (pulses). doesn't make sense.
////    OCR0AH = 0xFF;  //
////    OCR0AL = 0xFF;
    
    //attiny10 output compare broken apparently
    //this still 960hz, with 100us or so pulse size (high is 100us, low is longer)
    //OCR0A = 100;
    
    
    //inline asm to load values into 16 bit register
    
        //; variables
        //; For 1 Hz output, the timer delay has to be 1/2 second (1/2 second on / 1/2 second off)
        //;  delay = OCR0A * 1024 * 8 / 8000000
        //;  for 1/2 second, OCR0A = 488 (0x01E8)
        //.EQU OCR0AHigh = 0x01  
        //.EQU OCR0ALow = 0xe8
    // in bash type: printf "%x\n" 488
        //.EQU OCR0AHigh = 0x02  
        //.EQU OCR0ALow = 0x08

       // ldi r17, OCR0AHigh //; Sets the output compare register value
        //ldi r16, OCR0ALow
    
    //this asm doesn't work (why?) //perhaps OCR0A is really just 8 bits on attiny10...?)
//////        asm volatile(
//////        "ldi r17, 0x02"
//////        "ldi r16, 0x08"
//////        "out OCR0AH, r17"
//////        "out OCR0AL, r16" 
//////        );
        
        //this asm works
//        asm volatile("nop\n\t"
//"nop\n\t"
//"nop\n\t"
//"nop\n\t"
//::);
        
    TIMSK0 |= _BV(OCIE0A); // enable Timer CTC interrupt
        
    // PB2 change to output
    DDRB = 1<<2;
    sei();

    while(1)
    {
        //handled by interrupt
   
    }
}