Electronics_Projects_2020/Prototyping_Board/pcb/pcb.kicad_pcb

(kicad_pcb (version 4) (host pcbnew 4.0.7-e2-6376~58~ubuntu16.04.1)

  (general
    (links 0)
    (no_connects 0)
    (area 104.572999 74.854999 178.510001 123.265001)
    (thickness 1.6)
    (drawings 1)
    (tracks 0)
    (zones 0)
    (modules 0)
    (nets 1)
  )

  (page USLetter)
  (title_block
    (title "Project Title")
  )

  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (44 Edge.Cuts user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.254)
    (user_trace_width 0.1524)
    (user_trace_width 0.254)
    (user_trace_width 0.3302)
    (user_trace_width 0.508)
    (user_trace_width 0.762)
    (user_trace_width 1.27)
    (trace_clearance 0.254)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.1524)
    (segment_width 0.1524)
    (edge_width 0.1524)
    (via_size 0.6858)
    (via_drill 0.3302)
    (via_min_size 0.6858)
    (via_min_drill 0.3302)
    (user_via 0.6858 0.3302)
    (user_via 0.762 0.4064)
    (user_via 0.8636 0.508)
    (uvia_size 0.6858)
    (uvia_drill 0.3302)
    (uvias_allowed no)
    (uvia_min_size 0)
    (uvia_min_drill 0)
    (pcb_text_width 0.1524)
    (pcb_text_size 1.016 1.016)
    (mod_edge_width 0.1524)
    (mod_text_size 1.016 1.016)
    (mod_text_width 0.1524)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.0762)
    (solder_mask_min_width 0.1016)
    (pad_to_paste_clearance -0.0762)
    (aux_axis_origin 0 0)
    (visible_elements FFFEDF7D)
    (pcbplotparams
      (layerselection 0x310fc_80000001)
      (usegerberextensions true)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory gerbers))
  )

  (net 0 "")

  (net_class Default "This is the default net class."
    (clearance 0.254)
    (trace_width 0.254)
    (via_dia 0.6858)
    (via_drill 0.3302)
    (uvia_dia 0.6858)
    (uvia_drill 0.3302)
  )

  (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n   SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n   WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n   MINIMUM SPACE - 0.006 INCH.\n   MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
    (effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
  )

)