Electronics_Projects_2020/60hz_Divider/code/xilinx/cpld_countertest10/counta.vhi

-- VHDL Instantiation Created from source file counta.vhd -- 01:07:15 07/14/2020
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT counta
	PORT(
		XSTALIN : IN std_logic;
		HZIN : IN std_logic;
		SWITCH : IN std_logic;          
		LED : OUT std_logic_vector(7 downto 0);
		TX : OUT std_logic
		);
	END COMPONENT;

	Inst_counta: counta PORT MAP(
		XSTALIN => ,
		HZIN => ,
		SWITCH => ,
		LED => ,
		TX => 
	);