You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

41 lines
1.2 KiB

4 years ago
  1. // File counter.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
  2. // vhd2vl settings:
  3. // * Verilog Module Declaration Style: 2001
  4. // vhd2vl is Free (libre) Software:
  5. // Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
  6. // http://www.ocean-logic.com
  7. // Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
  8. // Modifications (C) 2010 Shankar Giri
  9. // Modifications Copyright (C) 2002-2017 Larry Doolittle
  10. // http://doolittle.icarus.com/~larry/vhd2vl/
  11. // Modifications (C) 2017 Rodrigo A. Melo
  12. //
  13. // vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
  14. // Verilog for correctness, ideally with a formal verification tool.
  15. //
  16. // You are welcome to redistribute vhd2vl under certain conditions.
  17. // See the license (GPLv2) file included with the source for details.
  18. // The result of translation follows. Its copyright status should be
  19. // considered unchanged from the original VHDL.
  20. // no timescale needed
  21. module counter(
  22. input wire CLK_IN,
  23. output wire [3:0] RLED
  24. );
  25. reg [3:0] pres_count; wire [3:0] next_count;
  26. assign RLED = pres_count;
  27. always @(posedge CLK_IN) begin
  28. pres_count <= pres_count + 1;
  29. end
  30. endmodule