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okokokok

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Your Name 4 years ago
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25 changed files with 70914 additions and 1 deletions
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  1. +1
    -1
      Door_Chime/docs/10.log
  2. BIN
      Door_Chime/docs/10.pdf
  3. +22
    -0
      Prototyping_Board/footprints/Barrier_Strip_1x3.kicad_mod
  4. +31
    -0
      Prototyping_Board/footprints/Fuseholder5x20_horiz_SemiClosed_Casing10x25mm.kicad_mod
  5. +254
    -0
      Prototyping_Board/footprints/KiCad-Logo_5mm_Copper_FMASK.kicad_mod
  6. +27
    -0
      Prototyping_Board/footprints/PinHeader_1x01_EDIT.kicad_mod
  7. +11568
    -0
      Prototyping_Board/pcb/EDIT_C.kicad_pcb
  8. +11568
    -0
      Prototyping_Board/pcb/EDIT_C.kicad_pcb-bak
  9. +33
    -0
      Prototyping_Board/pcb/EDIT_C.pro
  10. +112
    -0
      Prototyping_Board/pcb/_autosave-pcb (copy 1).kicad_pcb
  11. +2544
    -0
      Prototyping_Board/pcb/edit.kicad_pcb
  12. +33
    -0
      Prototyping_Board/pcb/edit.pro
  13. +12792
    -0
      Prototyping_Board/pcb/edit_b.kicad_pcb
  14. +12792
    -0
      Prototyping_Board/pcb/edit_b.kicad_pcb-bak
  15. +3
    -0
      Prototyping_Board/pcb/fp-lib-table
  16. +2207
    -0
      Prototyping_Board/pcb/gerbers/EDIT_C-B.SilkS.gbo
  17. +2728
    -0
      Prototyping_Board/pcb/gerbers/EDIT_C-Back.gbl
  18. +6607
    -0
      Prototyping_Board/pcb/gerbers/EDIT_C-F.SilkS.gto
  19. +6776
    -0
      Prototyping_Board/pcb/gerbers/EDIT_C-Front.gtl
  20. +640
    -0
      Prototyping_Board/pcb/gerbers/EDIT_C.drl
  21. +117
    -0
      Prototyping_Board/pcb/pcb.kicad_pcb
  22. +41
    -0
      Prototyping_Board/pcb/pcb.pro
  23. +17
    -0
      Prototyping_Board/pcb/pcb.sch
  24. +1
    -0
      Prototyping_Board/resources/High-density-proto-board
  25. BIN
      Prototyping_Board/resources/mikes_electric_boards.pdf

+ 1
- 1
Door_Chime/docs/10.log View File

@ -1,4 +1,4 @@
This is pdfTeX, Version 3.14159265-2.6-1.40.17 (TeX Live 2016/Debian) (preloaded format=pdflatex 2019.8.17) 6 MAR 2020 00:00
This is pdfTeX, Version 3.14159265-2.6-1.40.17 (TeX Live 2016/Debian) (preloaded format=pdflatex 2019.8.17) 10 MAR 2020 02:02
entering extended mode entering extended mode
restricted \write18 enabled. restricted \write18 enabled.
%&-line parsing enabled. %&-line parsing enabled.

BIN
Door_Chime/docs/10.pdf View File


+ 22
- 0
Prototyping_Board/footprints/Barrier_Strip_1x3.kicad_mod View File

@ -0,0 +1,22 @@
(module footprints:Barrier_Strip_1x3 (layer F.Cu) (tedit 5E16D6E2)
(fp_text reference J47 (at -7 16) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Screw_Terminal_01x03 (at 1 10) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user ED2946-ND (at 3 13) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 16 15) (end 16 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start -9.5 15) (end 16 15) (layer F.SilkS) (width 0.15))
(fp_line (start 9.5 2.5) (end -3 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.5 2.5) (end 16 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start -9.5 14.5) (end -9.5 15) (layer F.SilkS) (width 0.15))
(fp_line (start -9.5 8.5) (end -9.5 14.5) (layer F.SilkS) (width 0.15))
(fp_line (start -9.5 2.5) (end -9.5 8.5) (layer F.SilkS) (width 0.15))
(fp_line (start -9.5 2.5) (end -3 2.5) (layer F.SilkS) (width 0.15))
(pad 3 thru_hole circle (at 11.5 5) (size 2.7 2.7) (drill 2) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 3.25 5) (size 2.7 2.7) (drill 2) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at -5 5) (size 2.7 2.7) (drill 2) (layers *.Cu *.Mask))
)

+ 31
- 0
Prototyping_Board/footprints/Fuseholder5x20_horiz_SemiClosed_Casing10x25mm.kicad_mod View File

@ -0,0 +1,31 @@
(module Fuse_Holders_and_Fuses:Fuseholder5x20_horiz_SemiClosed_Casing10x25mm (layer F.Cu) (tedit 0)
(descr "Fuseholder, 5x20, Semi closed, horizontal, Casing 10x25mm,")
(tags "Fuseholder, 5x20, Semi closed, horizontal, Casing 10x25mm, Sicherungshalter, halbgeschlossen,")
(fp_text reference F1 (at 0 -7.62) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Fuse (at 1.27 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -11.99896 -5.00126) (end -11.99896 -1.89992) (layer F.SilkS) (width 0.15))
(fp_line (start 11.99896 -5.00126) (end -11.99896 -5.00126) (layer F.SilkS) (width 0.15))
(fp_line (start 11.99896 5.00126) (end 11.99896 1.89992) (layer F.SilkS) (width 0.15))
(fp_line (start -11.99896 5.00126) (end 11.99896 5.00126) (layer F.SilkS) (width 0.15))
(fp_line (start -11.99896 1.89992) (end -11.99896 5.00126) (layer F.SilkS) (width 0.15))
(fp_line (start 11.99896 -1.89992) (end 11.99896 -5.00126) (layer F.SilkS) (width 0.15))
(fp_line (start -9.99998 -2.49936) (end -9.99998 -1.89992) (layer F.SilkS) (width 0.15))
(fp_line (start 9.99998 -2.49936) (end -9.99998 -2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start 9.99998 2.49936) (end 9.99998 1.89992) (layer F.SilkS) (width 0.15))
(fp_line (start -9.99998 2.49936) (end 9.99998 2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -9.99998 1.89992) (end -9.99998 2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start 9.99998 -1.89992) (end 9.99998 -2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start 4.50088 -2.49936) (end 4.50088 2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -4.50088 -2.49936) (end -4.50088 2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -4.50088 0) (end 4.50088 0) (layer F.SilkS) (width 0.15))
(fp_line (start 5.99948 -5.00126) (end 5.99948 -2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start 5.99948 5.00126) (end 5.99948 2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -5.99948 5.00126) (end -5.99948 2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -5.99948 -2.49936) (end -5.99948 -5.00126) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole oval (at -11.00074 0 270) (size 2.49936 4.0005) (drill 1.50114) (layers *.Cu *.Mask))
(pad 2 thru_hole oval (at 11.00074 0 270) (size 2.49936 4.0005) (drill 1.50114) (layers *.Cu *.Mask))
)

+ 254
- 0
Prototyping_Board/footprints/KiCad-Logo_5mm_Copper_FMASK.kicad_mod View File

@ -0,0 +1,254 @@
(module Symbol:KiCad-Logo_5mm_Copper (layer F.Cu) (tedit 5E6DCC40)
(descr "KiCad Logo")
(tags "Logo KiCad")
(attr virtual)
(fp_text reference REF1001 (at 0 -3.7) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value KiCad-Logo_5mm_Copper (at 0 2.8) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -6.4 2) (end -6.4 -3) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.4 -3) (end 6.4 -3) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.4 -3) (end 6.4 2) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.4 2) (end -6.4 2) (layer F.CrtYd) (width 0.05))
(fp_poly (pts (xy -2.9464 -2.510946) (xy -2.935535 -2.397007) (xy -2.903918 -2.289384) (xy -2.853015 -2.190385)
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+ 117
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Prototyping_Board/pcb/pcb.kicad_pcb View File

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(kicad_pcb (version 4) (host pcbnew 4.0.7-e2-6376~58~ubuntu16.04.1)
(general
(links 0)
(no_connects 0)
(area 104.572999 74.854999 178.510001 123.265001)
(thickness 1.6)
(drawings 1)
(tracks 0)
(zones 0)
(modules 0)
(nets 1)
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(page USLetter)
(title_block
(title "Project Title")
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(44 Edge.Cuts user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.254)
(user_trace_width 0.1524)
(user_trace_width 0.254)
(user_trace_width 0.3302)
(user_trace_width 0.508)
(user_trace_width 0.762)
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(solder_mask_min_width 0.1016)
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(visible_elements FFFEDF7D)
(pcbplotparams
(layerselection 0x310fc_80000001)
(usegerberextensions true)
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(linewidth 0.100000)
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(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
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(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory gerbers))
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(net 0 "")
(net_class Default "This is the default net class."
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(gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
(effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
)
)

+ 41
- 0
Prototyping_Board/pcb/pcb.pro View File

@ -0,0 +1,41 @@
update=Tue 11 Oct 2016 05:25:07 PM PDT
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.016000000000
PcbTextSizeH=1.016000000000
PcbTextThickness=0.152400000000
ModuleTextSizeV=1.016000000000
ModuleTextSizeH=1.016000000000
ModuleTextSizeThickness=0.152400000000
SolderMaskClearance=0.003000000000
SolderMaskMinWidth=0.004000000000
DrawSegmentWidth=0.152400000000
BoardOutlineThickness=0.152400000000
ModuleOutlineThickness=0.152400000000
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=50
[general]
version=1

+ 17
- 0
Prototyping_Board/pcb/pcb.sch View File

@ -0,0 +1,17 @@
EESchema Schematic File Version 2
LIBS:power
EELAYER 25 0
EELAYER END
$Descr USLetter 11000 8500
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$EndSCHEMATC

+ 1
- 0
Prototyping_Board/resources/High-density-proto-board

@ -0,0 +1 @@
Subproject commit fdb49a08c1e282aa200a7544f6cc23ffd50b3639

BIN
Prototyping_Board/resources/mikes_electric_boards.pdf View File


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