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85 lines
2.8 KiB
85 lines
2.8 KiB
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\documentclass[11pt]{article}
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%Gummi|065|=)
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\usepackage{graphicx}
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\usepackage{caption}
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\usepackage{xcolor}
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\usepackage[vcentering,dvips]{geometry}
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\geometry{papersize={6in,9in},total={4.5in,6.8in}}
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\title{\textbf{}}
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\author{Steak Electronics}
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\date{}
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\begin{document}
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%\maketitle
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\tableofcontents
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\textcolor{green!60!blue!70}{
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\section{60Hz Divider}}
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\subsection{Overview}
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Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
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The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD}
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\subsection{Initial Notes: Counting the Hz}
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pseudo code goal:
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\begin{verbatim}
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Using 1Hz signal
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Start counting 1MHz every 1Hz
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when next cycle is received,
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display count
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start counting again
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\end{verbatim}
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That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
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4553 x 5
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74hct132
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1MHz clock (or 6MHz clock), or some variation thereof
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jk flip flop
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74376 - quad jk flip flop
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7476 - jk flip flop
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1mhz clk will be main counter,
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6 hz or 1 hz will be latch / reset
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I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
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\subsection{MAX7219 8 digit 7 LED segment Display Driver}
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Basic code tested with this was the LedControl arduino library.
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\begin{verbatim}
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/*
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Now we need a LedControl to work with.
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***** These pin numbers will probably not work with your hardware *****
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pin 12 is connected to the DataIn
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pin 11 is connected to the CLK
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pin 10 is connected to LOAD
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We have only a single MAX72XX.
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*/
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\end{verbatim}
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Some of the lines have to be edited to allow for all digits to be read, and
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also to lower intensity of display. I think also a component package (dark
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grey clear plastic bag) in front of the leds with intensity 1 is about right.
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\subsection{CPLD Programming}
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Using the XC9500XL series. This chip has some limitations - which are good.
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As you get faster clocks, you need bigger registers to handle parsing the clocks.
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bigger registers, use more power.
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\subsubsection{6KHz clock}
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Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
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\end{document}
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