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302 lines
8.5 KiB
302 lines
8.5 KiB
#include <xc.h>
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#include <avr/io.h>
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//this req'd for (and before calling) delay
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//see delay.h
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//compiler optimizations must also be enabled
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#define F_CPU 8000000
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#include <util/delay.h>
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#include <avr/interrupt.h>
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//#include <avr/sleep.h>
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//#include <util/atomic.h>
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//#include <avr/wdt.h>
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//tests5 tested and works (at ~950hz). unplug cable to programmer to see pin 4 active.
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//however...
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//tests6 DEADEND
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//never worked right. giving up and using delay.
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//reference: https://www.avrfreaks.net/forum/sample-project-attiny10
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//https://blog.podkalicki.com/attiny13-blinky-with-timer-compa/
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//watchdog is too slow and inaccurate to get 6000Hz
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//ISR(TIM0_COMPA_vect)
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//{
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// // Toggle PB2 Hi/Low depending on current state
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// PINB = 1<<2;
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// TIFR0 |= 1<<OCF0A; //clear flag (is this required here? documentation unclear)
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// //PORTB ^= _BV(LED_PIN); // toggle LED pin
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//}
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/*
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Delay in powerdown mode. Wake up by watchdog interrupt.
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* //NOTE: see earlier code, e.g. tests3 in attiny10 elec projects 2020
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*/
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/*
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void delay_power_down_wdt(uint8_t wdto)
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{
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wdt_reset();
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wdt_enable(wdto);
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WDTCSR |= (1<<WDIE);
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//so far (with 128Khz clk) this sleep will be about 30-40 seconds.
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//(however, I'll add the below to)
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//adjust sleep speed here:
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// 0110 is 1hz at 128KHz
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//WDTCSR |= (0<< WDP3);
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//WDTCSR |= (1<< WDP2);
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//WDTCSR |= (1<< WDP1);
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//WDTCSR |= (0<< WDP0);
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set_sleep_mode(SLEEP_MODE_PWR_DOWN);
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sleep_enable();
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// Make sure interrups are enabled and the I flag is restored
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NONATOMIC_BLOCK(NONATOMIC_RESTORESTATE)
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{
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sleep_cpu();
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wdt_disable();
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}
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sleep_disable();
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}
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*/
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int main(void)
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{
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//// //Write CCP (to enable changing clock)
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CCP = 0xD8;
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//// //change CLK to 128KHz
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// CLKMSR = 0b01;
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//change clk to 8mhz
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CLKMSR = 0b00;
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//clock prescaler from divide by 8 (defualt) to none
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//CLKPS0 = 0x0;
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//CLKPS1 = 0x0;
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//Just omit the bits that are reserved, see also clkmsr which is 2 bit active
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// 8 bit inactive
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CLKPSR = 0b0000;
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//notes: test results (osccal is 8 bit)
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// osccal | hz output
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// 0xe6 10khz
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// 0x06 3.58khz
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// 0x0F 3.83Khz
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// 0x2F 4.62Khz
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// 0x5F 5.84Khz
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// 0x65 6.003KHz -winrar (for this chip))
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// 0x8F 7.27Khz
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OSCCAL = 0x65;
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//////// OCR0A = 0;
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//////// TCNT0 = 0;
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//////// TCCR0A = 0;
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//////// TCCR0B = 0;
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////////
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//////// TCCR0A |= _BV(WGM01); // set timer counter mode to CTC
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//////// // TCCR0B |= _BV(CS02)|_BV(CS00); // set prescaler to 1024 (CLK=1200000Hz/1024/256=4.57Hz, 0.22s)
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//////// TCCR0B |= _BV(CS00); // set prescaler to 1 (CLK=1MHz/1)
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//OCR0A is 16 bits. in ASM it must be loaded separately.
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//in C, it can be loaded > 256? (test)
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//520 about 950hz, 25us wide pulse
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//OCR0A = 520; // with one timer, ever 166.667hz we want to count once (3000hz)
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//OCR0A = 1; //475hz
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//this goes to 475hz (pulses). doesn't make sense.
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//// OCR0AH = 0xFF; //
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//// OCR0AL = 0xFF;
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//attiny10 output compare broken apparently
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//this still 960hz, with 100us or so pulse size (high is 100us, low is longer)
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//OCR0A = 100;
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//inline asm to load values into 16 bit register
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//; variables
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//; For 1 Hz output, the timer delay has to be 1/2 second (1/2 second on / 1/2 second off)
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//; delay = OCR0A * 1024 * 8 / 8000000
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//; for 1/2 second, OCR0A = 488 (0x01E8)
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//.EQU OCR0AHigh = 0x01
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//.EQU OCR0ALow = 0xe8
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// in bash type: printf "%x\n" 488
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//.EQU OCR0AHigh = 0x02
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//.EQU OCR0ALow = 0x08
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// ldi r17, OCR0AHigh //; Sets the output compare register value
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//ldi r16, OCR0ALow
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//this asm doesn't work (why?) //perhaps OCR0A is really just 8 bits on attiny10...?)
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////// asm volatile(
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////// "ldi r17, 0x02"
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////// "ldi r16, 0x08"
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////// "out OCR0AH, r17"
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////// "out OCR0AL, r16"
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////// );
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//this asm works
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// asm volatile("nop\n\t"
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//"nop\n\t"
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//"nop\n\t"
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//"nop\n\t"
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//::);
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////////
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//////// TIMSK0 |= _BV(OCIE0A); // enable Timer CTC interrupt
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////////
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// PB2 change to output
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DDRB = 1<<2;
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//// sei();
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int x = 0;
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while(1)
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{
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//this goes about 60.3KHz.
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//experiment FAIL
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//will just buy a 6KHz oscillator.
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PINB = 1<<2;
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//EDIT: disabled optimization in mplab (level 0)
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//and ended up geting much slower IO
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//asm("nop;");
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//for(x=0;x<10;x++){
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//note it's _delay_us not delay_us
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//delay_us(1) is 44.3KHz
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//_delay_us(8); //9 is 6.4KHz, 8 is roughly 7.2KHz
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//delay_us(10) is 5.8KHz
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//not much granularity there...)
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//so adding the following...
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if( x == 3){
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_delay_us(4);//these two are 5.98 or so KHz
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x = 0;
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goto jump;
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}
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//NOTE: the above ends up causing an ugly looking clock. may not matter
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//for fpga clocking off of rising edge, BUT, it is ugly, should remove,
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//and just do single delay. Will do in part 9.
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x++;
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jump:
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//in combination with the jump, gives closer to 6KHz
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_delay_us(8);
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///below didn't work out, so using osccal
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//bit convuluted anyways
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/*if( x == 4){
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_delay_us(1);
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//x = 0;
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goto jump;
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}
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if( x == 8){
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_delay_us(2);
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x = 0;
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goto jump;
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}
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x++;
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jump:
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//in combination with the jump, gives closer to 6KHz
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_delay_us(8);*/
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//the above idles at 5.98 - 5.99KHz.
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//best so far.
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//Now, calibrate oscillator with OSCCAL
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//if more accuracy desired.
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//or adjust if clause above
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//tried to make my own delay in ASM, BUT
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//compiler keeps optimizing it out (even w/out optimization enabled)
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//... some other flag may be culprit. So instead will use delay_us. Two delay
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//functions are delay_ms and delay_us. see headers at top and delay.h)
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/* __asm__("mov r16, r17;"
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"mov r17, r16;"
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"inc r16;"
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"dec r16;"
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"mov r16, r17;"
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"mov r17, r16;"
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"inc r16;"
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"dec r16;"
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"clr r16;"
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"clr r17;"
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"clr r18;"
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"clr r19;"
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"clr r20;"
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"clr r21;"
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"clr r22;"
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"clr r23;"
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"mov r16, r17;"
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"mov r17, r16;"
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"inc r16;"
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"dec r16;"
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"mov r16, r17;"
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"mov r17, r16;"
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"clr r16;"
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"clr r17;"
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"clr r18;"
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"clr r19;"
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"clr r20;"
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"clr r21;"
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"clr r22;"
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"clr r23;"
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"mov r16, r17;"
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"mov r17, r16;"
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"inc r16;"
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"dec r16;"
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"mov r16, r17;"
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"mov r17, r16;"
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);*/
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//mplab delay is:
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/** \ingroup util_delay_basic
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Delay loop using an 8-bit counter \c __count, so up to 256
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iterations are possible. (The value 256 would have to be passed
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as 0.) The loop executes three CPU cycles per iteration, not
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including the overhead the compiler needs to setup the counter
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register.
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Thus, at a CPU speed of 1 MHz, delays of up to 768 microseconds
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can be achieved.
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*/
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//////////void
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//////////_delay_loop_1(uint8_t __count)
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//////////{
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////////// __asm__ volatile (
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////////// "1: dec %0" "\n\t"
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////////// "brne 1b"
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////////// : "=r" (__count)
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////////// : "0" (__count)
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////////// );
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//////////}
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//////////
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//////////
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//ignore below
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// asm("nop;""nop;""nop;""nop;""nop;"
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//"nop;""nop;"//"nop;""nop;"//"nop;""nop;"
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//);
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//}//just this asm block is about 121.22KHz
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}
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}
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