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41 lines
1.2 KiB
41 lines
1.2 KiB
// File counter.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
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// vhd2vl settings:
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// * Verilog Module Declaration Style: 2001
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// vhd2vl is Free (libre) Software:
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// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
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// http://www.ocean-logic.com
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// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
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// Modifications (C) 2010 Shankar Giri
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// Modifications Copyright (C) 2002-2017 Larry Doolittle
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// http://doolittle.icarus.com/~larry/vhd2vl/
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// Modifications (C) 2017 Rodrigo A. Melo
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//
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// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
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// Verilog for correctness, ideally with a formal verification tool.
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//
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// You are welcome to redistribute vhd2vl under certain conditions.
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// See the license (GPLv2) file included with the source for details.
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// The result of translation follows. Its copyright status should be
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// considered unchanged from the original VHDL.
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// no timescale needed
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module counter(
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input wire CLK_IN,
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output wire [3:0] RLED
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);
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reg [3:0] pres_count; wire [3:0] next_count;
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assign RLED = pres_count;
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always @(posedge CLK_IN) begin
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pres_count <= pres_count + 1;
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end
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endmodule
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