You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
812 lines
40 KiB
812 lines
40 KiB
|
|
cpldfit: version P.20131013 Xilinx Inc.
|
|
Fitter Report
|
|
Design Name: counta Date: 8- 4-2020, 0:40AM
|
|
Device Used: XC9572XL-5-VQ44
|
|
Fitting Status: Successful
|
|
|
|
************************* Mapped Resource Summary **************************
|
|
|
|
Macrocells Product Terms Function Block Registers Pins
|
|
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
|
|
42 /72 ( 58%) 227 /360 ( 63%) 86 /216 ( 40%) 42 /72 ( 58%) 11 /34 ( 32%)
|
|
|
|
** Function Block Resources **
|
|
|
|
Function Mcells FB Inps Pterms IO
|
|
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
|
FB1 7/18 25/54 47/90 7/ 9
|
|
FB2 11/18 22/54 57/90 0/ 9
|
|
FB3 18/18* 22/54 84/90 2/ 9
|
|
FB4 6/18 17/54 39/90 2/ 7
|
|
----- ----- ----- -----
|
|
42/72 86/216 227/360 11/34
|
|
|
|
* - Resource is exhausted
|
|
|
|
** Global Control Resources **
|
|
|
|
Global clock net(s) unused.
|
|
Global output enable net(s) unused.
|
|
Global set/reset net(s) unused.
|
|
|
|
** Pin Resources **
|
|
|
|
Signal Type Required Mapped | Pin Type Used Total
|
|
------------------------------------|------------------------------------
|
|
Input : 2 2 | I/O : 8 28
|
|
Output : 9 9 | GCK/IO : 3 3
|
|
Bidirectional : 0 0 | GTS/IO : 0 2
|
|
GCK : 0 0 | GSR/IO : 0 1
|
|
GTS : 0 0 |
|
|
GSR : 0 0 |
|
|
---- ----
|
|
Total 11 11
|
|
|
|
** Power Data **
|
|
|
|
There are 42 macrocells in high performance mode (MCHP).
|
|
There are 0 macrocells in low power mode (MCLP).
|
|
End of Mapped Resource Summary
|
|
************************** Errors and Warnings ***************************
|
|
|
|
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
|
|
use the default filename of 'counta.ise'.
|
|
************************* Summary of Mapped Logic ************************
|
|
|
|
** 9 Outputs **
|
|
|
|
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
|
|
Name Pts Inps No. Type Use Mode Rate State
|
|
LED<0> 7 10 FB1_6 41 I/O O STD FAST RESET
|
|
LED<1> 7 10 FB1_8 42 I/O O STD FAST RESET
|
|
LED<2> 7 10 FB1_9 43 GCK/I/O O STD FAST RESET
|
|
LED<3> 7 10 FB1_11 44 GCK/I/O O STD FAST RESET
|
|
LED<4> 7 10 FB1_14 1 GCK/I/O O STD FAST RESET
|
|
LED<5> 7 10 FB1_15 2 I/O O STD FAST RESET
|
|
LED<6> 5 12 FB1_17 3 I/O O STD FAST RESET
|
|
LED<7> 4 12 FB3_2 5 I/O O STD FAST RESET
|
|
TX 6 9 FB3_5 6 I/O O STD FAST RESET
|
|
|
|
** 33 Buried Nodes **
|
|
|
|
Signal Total Total Loc Pwr Reg Init
|
|
Name Pts Inps Mode State
|
|
clkcounta<9> 5 14 FB2_8 STD RESET
|
|
clkcounta<8> 5 13 FB2_9 STD RESET
|
|
clkcounta<7> 5 12 FB2_10 STD RESET
|
|
clkcounta<6> 5 11 FB2_11 STD RESET
|
|
clkcounta<5> 5 10 FB2_12 STD RESET
|
|
clkcounta<4> 5 9 FB2_13 STD RESET
|
|
clkcounta<3> 5 8 FB2_14 STD RESET
|
|
clkcounta<12> 5 17 FB2_15 STD RESET
|
|
clkcounta<11> 5 16 FB2_16 STD RESET
|
|
clkcounta<10> 5 15 FB2_17 STD RESET
|
|
storecounta<13> 7 10 FB2_18 STD RESET
|
|
alreadystoredcnt<0> 3 7 FB3_1 STD RESET
|
|
uartskip<0> 3 7 FB3_3 STD RESET
|
|
clkcounta<0> 3 5 FB3_4 STD RESET
|
|
uartctr<4> 4 12 FB3_6 STD RESET
|
|
uartctr<3> 4 12 FB3_7 STD RESET
|
|
uartctr<2> 4 12 FB3_8 STD RESET
|
|
uartctr<1> 4 12 FB3_9 STD RESET
|
|
uartctr<0> 4 12 FB3_10 STD RESET
|
|
clkcounta<2> 5 7 FB3_11 STD RESET
|
|
clkcounta<1> 5 6 FB3_12 STD RESET
|
|
storecounta<2> 6 9 FB3_13 STD RESET
|
|
storecounta<1> 6 9 FB3_14 STD RESET
|
|
resetclk<0> 2 3 FB3_15 STD RESET
|
|
storecounta<5> 7 10 FB3_16 STD RESET
|
|
storecounta<4> 7 10 FB3_17 STD RESET
|
|
storecounta<3> 7 10 FB3_18 STD RESET
|
|
storecounta<14> 7 10 FB4_1 STD RESET
|
|
storecounta<18> 6 8 FB4_13 STD RESET
|
|
storecounta<17> 6 9 FB4_14 STD RESET
|
|
storecounta<16> 6 9 FB4_15 STD RESET
|
|
storecounta<6> 7 10 FB4_17 STD RESET
|
|
storecounta<15> 7 10 FB4_18 STD RESET
|
|
|
|
** 2 Inputs **
|
|
|
|
Signal Loc Pin Pin Pin
|
|
Name No. Type Use
|
|
XSTALIN FB4_5 20 I/O I
|
|
HZIN FB4_8 21 I/O I
|
|
|
|
Legend:
|
|
Pin No. - ~ - User Assigned
|
|
************************** Function Block Details ************************
|
|
Legend:
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
Imp Pt - Product terms imported from other macrocells
|
|
Exp Pt - Product terms exported to other macrocells
|
|
in direction shown
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
Loc - Location where logic was mapped in device
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
O - Output GTS - Global Output Enable
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
X - Signal used as input to the macrocell logic.
|
|
Pin No. - ~ - User Assigned
|
|
*********************************** FB1 ***********************************
|
|
Number of function block inputs used/remaining: 25/29
|
|
Number of signals used by logic mapping into function block: 25
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB1_1 (b)
|
|
(unused) 0 0 0 5 FB1_2 39 I/O
|
|
(unused) 0 0 0 5 FB1_3 (b)
|
|
(unused) 0 0 0 5 FB1_4 (b)
|
|
(unused) 0 0 \/1 4 FB1_5 40 I/O (b)
|
|
LED<0> 7 2<- 0 0 FB1_6 41 I/O O
|
|
(unused) 0 0 /\1 4 FB1_7 (b) (b)
|
|
LED<1> 7 2<- 0 0 FB1_8 42 I/O O
|
|
LED<2> 7 4<- /\2 0 FB1_9 43 GCK/I/O O
|
|
(unused) 0 0 /\4 1 FB1_10 (b) (b)
|
|
LED<3> 7 2<- 0 0 FB1_11 44 GCK/I/O O
|
|
(unused) 0 0 /\2 3 FB1_12 (b) (b)
|
|
(unused) 0 0 \/2 3 FB1_13 (b) (b)
|
|
LED<4> 7 2<- 0 0 FB1_14 1 GCK/I/O O
|
|
LED<5> 7 2<- 0 0 FB1_15 2 I/O O
|
|
(unused) 0 0 /\2 3 FB1_16 (b) (b)
|
|
LED<6> 5 0 0 0 FB1_17 3 I/O O
|
|
(unused) 0 0 0 5 FB1_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: HZIN 10: XSTALIN 18: resetclk<0>
|
|
2: LED<0> 11: alreadystoredcnt<0> 19: storecounta<13>
|
|
3: LED<1> 12: clkcounta<4> 20: uartctr<0>
|
|
4: LED<2> 13: clkcounta<5> 21: uartctr<1>
|
|
5: LED<3> 14: clkcounta<6> 22: uartctr<2>
|
|
6: LED<4> 15: clkcounta<7> 23: uartctr<3>
|
|
7: LED<5> 16: clkcounta<8> 24: uartctr<4>
|
|
8: LED<6> 17: clkcounta<9> 25: uartskip<0>
|
|
9: LED<7>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LED<0> XXX....XXXXX.....X......X............... 10
|
|
LED<1> X.XX...XXXX.X....X......X............... 10
|
|
LED<2> X..XX..XXXX..X...X......X............... 10
|
|
LED<3> X...XX.XXXX...X..X......X............... 10
|
|
LED<4> X....XXXXXX....X.X......X............... 10
|
|
LED<5> X.....XXXXX.....XXX.....X............... 10
|
|
LED<6> X......XXXX......X.XXXXXX............... 12
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB2 ***********************************
|
|
Number of function block inputs used/remaining: 22/32
|
|
Number of signals used by logic mapping into function block: 22
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\2 3 FB2_1 (b) (b)
|
|
(unused) 0 0 0 5 FB2_2 29 I/O
|
|
(unused) 0 0 0 5 FB2_3 (b)
|
|
(unused) 0 0 0 5 FB2_4 (b)
|
|
(unused) 0 0 0 5 FB2_5 30 I/O
|
|
(unused) 0 0 0 5 FB2_6 31 I/O
|
|
(unused) 0 0 0 5 FB2_7 (b)
|
|
clkcounta<9> 5 0 0 0 FB2_8 32 I/O (b)
|
|
clkcounta<8> 5 0 0 0 FB2_9 33 GSR/I/O (b)
|
|
clkcounta<7> 5 0 0 0 FB2_10 (b) (b)
|
|
clkcounta<6> 5 0 0 0 FB2_11 34 GTS/I/O (b)
|
|
clkcounta<5> 5 0 0 0 FB2_12 (b) (b)
|
|
clkcounta<4> 5 0 0 0 FB2_13 (b) (b)
|
|
clkcounta<3> 5 0 0 0 FB2_14 36 GTS/I/O (b)
|
|
clkcounta<12> 5 0 0 0 FB2_15 37 I/O (b)
|
|
clkcounta<11> 5 0 0 0 FB2_16 (b) (b)
|
|
clkcounta<10> 5 0 0 0 FB2_17 38 I/O (b)
|
|
storecounta<13> 7 2<- 0 0 FB2_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: HZIN 9: clkcounta<12> 16: clkcounta<7>
|
|
2: LED<6> 10: clkcounta<1> 17: clkcounta<8>
|
|
3: LED<7> 11: clkcounta<2> 18: clkcounta<9>
|
|
4: XSTALIN 12: clkcounta<3> 19: resetclk<0>
|
|
5: alreadystoredcnt<0> 13: clkcounta<4> 20: storecounta<13>
|
|
6: clkcounta<0> 14: clkcounta<5> 21: storecounta<14>
|
|
7: clkcounta<10> 15: clkcounta<6> 22: uartskip<0>
|
|
8: clkcounta<11>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
clkcounta<9> X..XXX...XXXXXXXXXX..................... 14
|
|
clkcounta<8> X..XXX...XXXXXXXX.X..................... 13
|
|
clkcounta<7> X..XXX...XXXXXXX..X..................... 12
|
|
clkcounta<6> X..XXX...XXXXXX...X..................... 11
|
|
clkcounta<5> X..XXX...XXXXX....X..................... 10
|
|
clkcounta<4> X..XXX...XXXX.....X..................... 9
|
|
clkcounta<3> X..XXX...XXX......X..................... 8
|
|
clkcounta<12> X..XXXXXXXXXXXXXXXX..................... 17
|
|
clkcounta<11> X..XXXXX.XXXXXXXXXX..................... 16
|
|
clkcounta<10> X..XXXX..XXXXXXXXXX..................... 15
|
|
storecounta<13> XXXXX.X...........XXXX.................. 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB3 ***********************************
|
|
Number of function block inputs used/remaining: 22/32
|
|
Number of signals used by logic mapping into function block: 22
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
alreadystoredcnt<0> 3 1<- /\3 0 FB3_1 (b) (b)
|
|
LED<7> 4 0 /\1 0 FB3_2 5 I/O O
|
|
uartskip<0> 3 0 0 2 FB3_3 (b) (b)
|
|
clkcounta<0> 3 0 \/1 1 FB3_4 (b) (b)
|
|
TX 6 1<- 0 0 FB3_5 6 I/O O
|
|
uartctr<4> 4 0 0 1 FB3_6 (b) (b)
|
|
uartctr<3> 4 0 0 1 FB3_7 (b) (b)
|
|
uartctr<2> 4 0 0 1 FB3_8 7 I/O (b)
|
|
uartctr<1> 4 0 \/1 0 FB3_9 8 I/O (b)
|
|
uartctr<0> 4 1<- \/2 0 FB3_10 (b) (b)
|
|
clkcounta<2> 5 2<- \/2 0 FB3_11 12 I/O (b)
|
|
clkcounta<1> 5 2<- \/2 0 FB3_12 (b) (b)
|
|
storecounta<2> 6 2<- \/1 0 FB3_13 (b) (b)
|
|
storecounta<1> 6 1<- 0 0 FB3_14 13 I/O (b)
|
|
resetclk<0> 2 0 \/3 0 FB3_15 14 I/O (b)
|
|
storecounta<5> 7 3<- \/1 0 FB3_16 18 I/O (b)
|
|
storecounta<4> 7 2<- 0 0 FB3_17 16 I/O (b)
|
|
storecounta<3> 7 3<- /\1 0 FB3_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: HZIN 9: clkcounta<2> 16: storecounta<6>
|
|
2: LED<6> 10: resetclk<0> 17: uartctr<0>
|
|
3: LED<7> 11: storecounta<1> 18: uartctr<1>
|
|
4: TX 12: storecounta<2> 19: uartctr<2>
|
|
5: XSTALIN 13: storecounta<3> 20: uartctr<3>
|
|
6: alreadystoredcnt<0> 14: storecounta<4> 21: uartctr<4>
|
|
7: clkcounta<0> 15: storecounta<5> 22: uartskip<0>
|
|
8: clkcounta<1>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
alreadystoredcnt<0> XXX.XX...X...........X.................. 7
|
|
LED<7> XXX.XX...X......XXXXXX.................. 12
|
|
uartskip<0> XXX.XX...X...........X.................. 7
|
|
clkcounta<0> X...XXX..X.............................. 5
|
|
TX XXXXXX...XX..........X.................. 9
|
|
uartctr<4> XXX.XX...X......XXXXXX.................. 12
|
|
uartctr<3> XXX.XX...X......XXXXXX.................. 12
|
|
uartctr<2> XXX.XX...X......XXXXXX.................. 12
|
|
uartctr<1> XXX.XX...X......XXXXXX.................. 12
|
|
uartctr<0> XXX.XX...X......XXXXXX.................. 12
|
|
clkcounta<2> X...XXXXXX.............................. 7
|
|
clkcounta<1> X...XXXX.X.............................. 6
|
|
storecounta<2> XXX.XX...X.XX........X.................. 9
|
|
storecounta<1> XXX.XX...XXX.........X.................. 9
|
|
resetclk<0> X...XX.................................. 3
|
|
storecounta<5> XXX.XX..XX....XX.....X.................. 10
|
|
storecounta<4> XXX.XX.X.X...XX......X.................. 10
|
|
storecounta<3> XXX.XXX..X..XX.......X.................. 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB4 ***********************************
|
|
Number of function block inputs used/remaining: 17/37
|
|
Number of signals used by logic mapping into function block: 17
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
storecounta<14> 7 4<- /\2 0 FB4_1 (b) (b)
|
|
(unused) 0 0 /\4 1 FB4_2 19 I/O (b)
|
|
(unused) 0 0 0 5 FB4_3 (b)
|
|
(unused) 0 0 0 5 FB4_4 (b)
|
|
(unused) 0 0 0 5 FB4_5 20 I/O I
|
|
(unused) 0 0 0 5 FB4_6 (b)
|
|
(unused) 0 0 0 5 FB4_7 (b)
|
|
(unused) 0 0 0 5 FB4_8 21 I/O I
|
|
(unused) 0 0 0 5 FB4_9 (b)
|
|
(unused) 0 0 0 5 FB4_10 (b)
|
|
(unused) 0 0 0 5 FB4_11 22 I/O
|
|
(unused) 0 0 \/3 2 FB4_12 (b) (b)
|
|
storecounta<18> 6 3<- \/2 0 FB4_13 (b) (b)
|
|
storecounta<17> 6 2<- \/1 0 FB4_14 23 I/O (b)
|
|
storecounta<16> 6 1<- 0 0 FB4_15 27 I/O (b)
|
|
(unused) 0 0 \/2 3 FB4_16 (b) (b)
|
|
storecounta<6> 7 2<- 0 0 FB4_17 28 I/O (b)
|
|
storecounta<15> 7 2<- 0 0 FB4_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: HZIN 7: clkcounta<11> 13: storecounta<16>
|
|
2: LED<0> 8: clkcounta<12> 14: storecounta<17>
|
|
3: LED<6> 9: clkcounta<3> 15: storecounta<18>
|
|
4: LED<7> 10: resetclk<0> 16: storecounta<6>
|
|
5: XSTALIN 11: storecounta<14> 17: uartskip<0>
|
|
6: alreadystoredcnt<0> 12: storecounta<15>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
storecounta<14> X.XXXXX..XXX....X....................... 10
|
|
storecounta<18> X.XXXX...X....X.X....................... 8
|
|
storecounta<17> X.XXXX...X...XX.X....................... 9
|
|
storecounta<16> X.XXXX...X..XX..X....................... 9
|
|
storecounta<6> XXXXXX..XX.....XX....................... 10
|
|
storecounta<15> X.XXXX.X.X.XX...X....................... 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
******************************* Equations ********************************
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),XSTALIN,'0','0');
|
|
LED_D(0) <= ((NOT LED(6) AND LED(0) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND LED(1) AND alreadystoredcnt(0))
|
|
OR (LED(6) AND LED(1) AND NOT HZIN)
|
|
OR (NOT LED(6) AND LED(0) AND alreadystoredcnt(0))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(4)));
|
|
|
|
FDCPE_LED1: FDCPE port map (LED(1),LED_D(1),XSTALIN,'0','0');
|
|
LED_D(1) <= ((NOT LED(6) AND LED(1) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND LED(2) AND alreadystoredcnt(0))
|
|
OR (LED(6) AND LED(2) AND NOT HZIN)
|
|
OR (NOT LED(6) AND LED(1) AND alreadystoredcnt(0))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(5)));
|
|
|
|
FDCPE_LED2: FDCPE port map (LED(2),LED_D(2),XSTALIN,'0','0');
|
|
LED_D(2) <= ((NOT LED(6) AND LED(2) AND alreadystoredcnt(0))
|
|
OR (NOT LED(6) AND LED(2) AND NOT HZIN)
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(6))
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND LED(3) AND alreadystoredcnt(0))
|
|
OR (LED(6) AND LED(3) AND NOT HZIN));
|
|
|
|
FDCPE_LED3: FDCPE port map (LED(3),LED_D(3),XSTALIN,'0','0');
|
|
LED_D(3) <= ((NOT LED(6) AND LED(3) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND LED(4) AND alreadystoredcnt(0))
|
|
OR (LED(6) AND LED(4) AND NOT HZIN)
|
|
OR (NOT LED(6) AND LED(3) AND alreadystoredcnt(0))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(7)));
|
|
|
|
FDCPE_LED4: FDCPE port map (LED(4),LED_D(4),XSTALIN,'0','0');
|
|
LED_D(4) <= ((NOT LED(6) AND LED(4) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND LED(5) AND alreadystoredcnt(0))
|
|
OR (LED(6) AND LED(5) AND NOT HZIN)
|
|
OR (NOT LED(6) AND LED(4) AND alreadystoredcnt(0))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(8)));
|
|
|
|
FDCPE_LED5: FDCPE port map (LED(5),LED_D(5),XSTALIN,'0','0');
|
|
LED_D(5) <= ((NOT LED(6) AND LED(5) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(13))
|
|
OR (LED(6) AND storecounta(13) AND NOT HZIN)
|
|
OR (NOT LED(6) AND LED(5) AND alreadystoredcnt(0))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(9)));
|
|
|
|
FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),XSTALIN,'0','0');
|
|
LED_T(6) <= ((NOT LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND NOT uartskip(0))
|
|
OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (LED(6) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartskip(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
uartctr(4) AND NOT HZIN));
|
|
|
|
FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),XSTALIN,'0','0');
|
|
LED_T(7) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
|
|
uartctr(2) AND uartctr(3) AND uartctr(4))
|
|
OR (NOT LED(7) AND LED(6) AND NOT alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4) AND NOT HZIN));
|
|
|
|
FDCPE_TX: FDCPE port map (TX,TX_D,XSTALIN,'0','0');
|
|
TX_D <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND NOT resetclk(0) AND storecounta(1))
|
|
OR (NOT LED(6) AND NOT resetclk(0) AND TX)
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(1) AND
|
|
HZIN)
|
|
OR (NOT LED(6) AND NOT alreadystoredcnt(0) AND HZIN AND TX));
|
|
|
|
FDCPE_alreadystoredcnt0: FDCPE port map (alreadystoredcnt(0),alreadystoredcnt_D(0),XSTALIN,'0','0');
|
|
alreadystoredcnt_D(0) <= ((LED(7) AND NOT LED(6) AND NOT resetclk(0) AND uartskip(0) AND
|
|
NOT HZIN)
|
|
OR (NOT alreadystoredcnt(0) AND NOT HZIN));
|
|
|
|
FDCPE_clkcounta0: FDCPE port map (clkcounta(0),clkcounta_D(0),XSTALIN,'0','0');
|
|
clkcounta_D(0) <= ((NOT resetclk(0) AND NOT clkcounta(0))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND NOT clkcounta(0)));
|
|
|
|
FDCPE_clkcounta1: FDCPE port map (clkcounta(1),clkcounta_D(1),XSTALIN,'0','0');
|
|
clkcounta_D(1) <= ((NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
NOT clkcounta(1))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND NOT clkcounta(0) AND
|
|
clkcounta(1))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND NOT clkcounta(1))
|
|
OR (NOT resetclk(0) AND NOT clkcounta(0) AND clkcounta(1)));
|
|
|
|
FTCPE_clkcounta2: FTCPE port map (clkcounta(2),clkcounta_T(2),XSTALIN,'0','0');
|
|
clkcounta_T(2) <= ((NOT resetclk(0) AND clkcounta(0) AND clkcounta(1))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1))
|
|
OR (alreadystoredcnt(0) AND resetclk(0) AND clkcounta(2))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(2)));
|
|
|
|
FTCPE_clkcounta3: FTCPE port map (clkcounta(3),clkcounta_T(3),XSTALIN,'0','0');
|
|
clkcounta_T(3) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(3))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(3))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2)));
|
|
|
|
FTCPE_clkcounta4: FTCPE port map (clkcounta(4),clkcounta_T(4),XSTALIN,'0','0');
|
|
clkcounta_T(4) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(4))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(4))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3)));
|
|
|
|
FTCPE_clkcounta5: FTCPE port map (clkcounta(5),clkcounta_T(5),XSTALIN,'0','0');
|
|
clkcounta_T(5) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(5))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(5))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3) AND clkcounta(4))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4)));
|
|
|
|
FTCPE_clkcounta6: FTCPE port map (clkcounta(6),clkcounta_T(6),XSTALIN,'0','0');
|
|
clkcounta_T(6) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(6))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(6))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
|
|
clkcounta(5)));
|
|
|
|
FTCPE_clkcounta7: FTCPE port map (clkcounta(7),clkcounta_T(7),XSTALIN,'0','0');
|
|
clkcounta_T(7) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(7))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(7))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
|
|
clkcounta(6))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
|
|
clkcounta(5) AND clkcounta(6)));
|
|
|
|
FTCPE_clkcounta8: FTCPE port map (clkcounta(8),clkcounta_T(8),XSTALIN,'0','0');
|
|
clkcounta_T(8) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(8))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(8))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
|
|
clkcounta(6) AND clkcounta(7))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
|
|
clkcounta(5) AND clkcounta(6) AND clkcounta(7)));
|
|
|
|
FTCPE_clkcounta9: FTCPE port map (clkcounta(9),clkcounta_T(9),XSTALIN,'0','0');
|
|
clkcounta_T(9) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(9))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(9))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
|
|
clkcounta(6) AND clkcounta(7) AND clkcounta(8))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
|
|
clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8)));
|
|
|
|
FTCPE_clkcounta10: FTCPE port map (clkcounta(10),clkcounta_T(10),XSTALIN,'0','0');
|
|
clkcounta_T(10) <= ((alreadystoredcnt(0) AND resetclk(0) AND
|
|
clkcounta(10))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(10))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
|
|
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
|
|
clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
|
|
clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
|
|
clkcounta(9)));
|
|
|
|
FTCPE_clkcounta11: FTCPE port map (clkcounta(11),clkcounta_T(11),XSTALIN,'0','0');
|
|
clkcounta_T(11) <= ((alreadystoredcnt(0) AND resetclk(0) AND
|
|
clkcounta(11))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(11))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(10) AND
|
|
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
|
|
clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
|
|
clkcounta(9))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(10) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
|
|
clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
|
|
clkcounta(8) AND clkcounta(9)));
|
|
|
|
FTCPE_clkcounta12: FTCPE port map (clkcounta(12),clkcounta_T(12),XSTALIN,'0','0');
|
|
clkcounta_T(12) <= ((alreadystoredcnt(0) AND resetclk(0) AND
|
|
clkcounta(12))
|
|
OR (resetclk(0) AND NOT HZIN AND clkcounta(12))
|
|
OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(10) AND
|
|
clkcounta(11) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
|
|
clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
|
|
clkcounta(8) AND clkcounta(9))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
|
|
clkcounta(10) AND clkcounta(11) AND clkcounta(1) AND clkcounta(2) AND
|
|
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
|
|
clkcounta(7) AND clkcounta(8) AND clkcounta(9)));
|
|
|
|
FDCPE_resetclk0: FDCPE port map (resetclk(0),resetclk_D(0),XSTALIN,'0','0');
|
|
resetclk_D(0) <= (NOT alreadystoredcnt(0) AND HZIN);
|
|
|
|
FDCPE_storecounta1: FDCPE port map (storecounta(1),storecounta_D(1),XSTALIN,'0','0');
|
|
storecounta_D(1) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND NOT resetclk(0) AND storecounta(2))
|
|
OR (NOT LED(6) AND NOT resetclk(0) AND storecounta(1))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(2) AND
|
|
HZIN)
|
|
OR (NOT LED(6) AND NOT alreadystoredcnt(0) AND storecounta(1) AND
|
|
HZIN));
|
|
|
|
FDCPE_storecounta2: FDCPE port map (storecounta(2),storecounta_D(2),XSTALIN,'0','0');
|
|
storecounta_D(2) <= ((NOT LED(6) AND storecounta(2))
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND storecounta(3))
|
|
OR (alreadystoredcnt(0) AND resetclk(0))
|
|
OR (resetclk(0) AND NOT HZIN));
|
|
|
|
FDCPE_storecounta3: FDCPE port map (storecounta(3),storecounta_D(3),XSTALIN,'0','0');
|
|
storecounta_D(3) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(3))
|
|
OR (NOT LED(6) AND storecounta(3) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(4))
|
|
OR (LED(6) AND storecounta(4) AND NOT HZIN)
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0)));
|
|
|
|
FDCPE_storecounta4: FDCPE port map (storecounta(4),storecounta_D(4),XSTALIN,'0','0');
|
|
storecounta_D(4) <= ((NOT LED(6) AND storecounta(4) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(5))
|
|
OR (LED(6) AND storecounta(5) AND NOT HZIN)
|
|
OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(4))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(1)));
|
|
|
|
FDCPE_storecounta5: FDCPE port map (storecounta(5),storecounta_D(5),XSTALIN,'0','0');
|
|
storecounta_D(5) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(5))
|
|
OR (NOT LED(6) AND storecounta(5) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(6))
|
|
OR (LED(6) AND storecounta(6) AND NOT HZIN)
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(2)));
|
|
|
|
FDCPE_storecounta6: FDCPE port map (storecounta(6),storecounta_D(6),XSTALIN,'0','0');
|
|
storecounta_D(6) <= ((NOT LED(6) AND storecounta(6) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND LED(0) AND alreadystoredcnt(0))
|
|
OR (LED(6) AND LED(0) AND NOT HZIN)
|
|
OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(6))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(3)));
|
|
|
|
FDCPE_storecounta13: FDCPE port map (storecounta(13),storecounta_D(13),XSTALIN,'0','0');
|
|
storecounta_D(13) <= ((NOT LED(6) AND storecounta(13) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(14))
|
|
OR (LED(6) AND storecounta(14) AND NOT HZIN)
|
|
OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(13))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(10)));
|
|
|
|
FDCPE_storecounta14: FDCPE port map (storecounta(14),storecounta_D(14),XSTALIN,'0','0');
|
|
storecounta_D(14) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(14))
|
|
OR (NOT LED(6) AND storecounta(14) AND NOT HZIN)
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(11))
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(15))
|
|
OR (LED(6) AND storecounta(15) AND NOT HZIN));
|
|
|
|
FDCPE_storecounta15: FDCPE port map (storecounta(15),storecounta_D(15),XSTALIN,'0','0');
|
|
storecounta_D(15) <= ((NOT LED(6) AND storecounta(15) AND NOT HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND alreadystoredcnt(0) AND storecounta(16))
|
|
OR (LED(6) AND storecounta(16) AND NOT HZIN)
|
|
OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(15))
|
|
OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(12)));
|
|
|
|
FDCPE_storecounta16: FDCPE port map (storecounta(16),storecounta_D(16),XSTALIN,'0','0');
|
|
storecounta_D(16) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND storecounta(17))
|
|
OR (NOT LED(6) AND storecounta(16))
|
|
OR (alreadystoredcnt(0) AND resetclk(0))
|
|
OR (resetclk(0) AND NOT HZIN));
|
|
|
|
FDCPE_storecounta17: FDCPE port map (storecounta(17),storecounta_D(17),XSTALIN,'0','0');
|
|
storecounta_D(17) <= ((NOT LED(6) AND NOT alreadystoredcnt(0) AND storecounta(17) AND
|
|
HZIN)
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND NOT resetclk(0) AND storecounta(18))
|
|
OR (NOT LED(6) AND NOT resetclk(0) AND storecounta(17))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(18) AND
|
|
HZIN));
|
|
|
|
FDCPE_storecounta18: FDCPE port map (storecounta(18),storecounta_D(18),XSTALIN,'0','0');
|
|
storecounta_D(18) <= ((LED(6) AND NOT alreadystoredcnt(0) AND HZIN)
|
|
OR (NOT alreadystoredcnt(0) AND storecounta(18) AND HZIN)
|
|
OR (LED(7) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartskip(0) AND NOT HZIN)
|
|
OR (LED(6) AND NOT resetclk(0))
|
|
OR (NOT resetclk(0) AND storecounta(18)));
|
|
|
|
FTCPE_uartctr0: FTCPE port map (uartctr(0),uartctr_T(0),XSTALIN,'0','0');
|
|
uartctr_T(0) <= ((LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
uartctr(4) AND NOT HZIN));
|
|
|
|
FTCPE_uartctr1: FTCPE port map (uartctr(1),uartctr_T(1),XSTALIN,'0','0');
|
|
uartctr_T(1) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND uartctr(0))
|
|
OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
uartctr(4) AND NOT HZIN));
|
|
|
|
FTCPE_uartctr2: FTCPE port map (uartctr(2),uartctr_T(2),XSTALIN,'0','0');
|
|
uartctr_T(2) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1))
|
|
OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
uartctr(4) AND NOT HZIN));
|
|
|
|
FTCPE_uartctr3: FTCPE port map (uartctr(3),uartctr_T(3),XSTALIN,'0','0');
|
|
uartctr_T(3) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
|
|
uartctr(2))
|
|
OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
uartctr(4) AND NOT HZIN));
|
|
|
|
FTCPE_uartctr4: FTCPE port map (uartctr(4),uartctr_T(4),XSTALIN,'0','0');
|
|
uartctr_T(4) <= ((LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
uartctr(3) AND uartctr(4))
|
|
OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
|
|
uartctr(2) AND uartctr(3))
|
|
OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
uartctr(4) AND NOT HZIN));
|
|
|
|
FTCPE_uartskip0: FTCPE port map (uartskip(0),uartskip_T(0),XSTALIN,'0','0');
|
|
uartskip_T(0) <= ((NOT LED(7) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
NOT uartskip(0))
|
|
OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
NOT resetclk(0) AND uartskip(0) AND NOT HZIN));
|
|
|
|
Register Legend:
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
Device : XC9572XL-5-VQ44
|
|
|
|
|
|
--------------------------------
|
|
/44 43 42 41 40 39 38 37 36 35 34 \
|
|
| 1 33 |
|
|
| 2 32 |
|
|
| 3 31 |
|
|
| 4 30 |
|
|
| 5 XC9572XL-5-VQ44 29 |
|
|
| 6 28 |
|
|
| 7 27 |
|
|
| 8 26 |
|
|
| 9 25 |
|
|
| 10 24 |
|
|
| 11 23 |
|
|
\ 12 13 14 15 16 17 18 19 20 21 22 /
|
|
--------------------------------
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
No. Name No. Name
|
|
1 LED<4> 23 KPR
|
|
2 LED<5> 24 TDO
|
|
3 LED<6> 25 GND
|
|
4 GND 26 VCC
|
|
5 LED<7> 27 KPR
|
|
6 TX 28 KPR
|
|
7 KPR 29 KPR
|
|
8 KPR 30 KPR
|
|
9 TDI 31 KPR
|
|
10 TMS 32 KPR
|
|
11 TCK 33 KPR
|
|
12 KPR 34 KPR
|
|
13 KPR 35 VCC
|
|
14 KPR 36 KPR
|
|
15 VCC 37 KPR
|
|
16 KPR 38 KPR
|
|
17 GND 39 KPR
|
|
18 KPR 40 KPR
|
|
19 KPR 41 LED<0>
|
|
20 XSTALIN 42 LED<1>
|
|
21 HZIN 43 LED<2>
|
|
22 KPR 44 LED<3>
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
VCC = Dedicated Power Pin
|
|
GND = Dedicated Ground Pin
|
|
TDI = Test Data In, JTAG pin
|
|
TDO = Test Data Out, JTAG pin
|
|
TCK = Test Clock, JTAG pin
|
|
TMS = Test Mode Select, JTAG pin
|
|
PROHIBITED = User reserved pin
|
|
**************************** Compiler Options ****************************
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
Device(s) Specified : xc9572xl-5-VQ44
|
|
Optimization Method : SPEED
|
|
Multi-Level Logic Optimization : ON
|
|
Ignore Timing Specifications : OFF
|
|
Default Register Power Up Value : LOW
|
|
Keep User Location Constraints : ON
|
|
What-You-See-Is-What-You-Get : OFF
|
|
Exhaustive Fitting : OFF
|
|
Keep Unused Inputs : OFF
|
|
Slew Rate : FAST
|
|
Power Mode : STD
|
|
Ground on Unused IOs : OFF
|
|
Set I/O Pin Termination : KEEPER
|
|
Global Clock Optimization : ON
|
|
Global Set/Reset Optimization : ON
|
|
Global Ouput Enable Optimization : ON
|
|
Input Limit : 54
|
|
Pterm Limit : 25
|