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418 lines
30 KiB
418 lines
30 KiB
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
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<h3 align='center'>Equations</h3>
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<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
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<tr><td>
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</td></tr><tr><td>
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********** Mapped Logic **********
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FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),XSTALIN,'0','0');
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<br/> LED_D(0) <= ((NOT LED(6) AND LED(0) AND NOT HZIN)
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND LED(1) AND alreadystoredcnt(0))
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<br/> OR (LED(6) AND LED(1) AND NOT HZIN)
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<br/> OR (NOT LED(6) AND LED(0) AND alreadystoredcnt(0))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(4)));
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</td></tr><tr><td>
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FDCPE_LED1: FDCPE port map (LED(1),LED_D(1),XSTALIN,'0','0');
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<br/> LED_D(1) <= ((NOT LED(6) AND LED(1) AND NOT HZIN)
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND LED(2) AND alreadystoredcnt(0))
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<br/> OR (LED(6) AND LED(2) AND NOT HZIN)
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<br/> OR (NOT LED(6) AND LED(1) AND alreadystoredcnt(0))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(5)));
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</td></tr><tr><td>
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FDCPE_LED2: FDCPE port map (LED(2),LED_D(2),XSTALIN,'0','0');
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<br/> LED_D(2) <= ((NOT LED(6) AND LED(2) AND alreadystoredcnt(0))
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<br/> OR (NOT LED(6) AND LED(2) AND NOT HZIN)
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(6))
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND LED(3) AND alreadystoredcnt(0))
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<br/> OR (LED(6) AND LED(3) AND NOT HZIN));
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</td></tr><tr><td>
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FDCPE_LED3: FDCPE port map (LED(3),LED_D(3),XSTALIN,'0','0');
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<br/> LED_D(3) <= ((NOT LED(6) AND LED(3) AND NOT HZIN)
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND LED(4) AND alreadystoredcnt(0))
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<br/> OR (LED(6) AND LED(4) AND NOT HZIN)
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<br/> OR (NOT LED(6) AND LED(3) AND alreadystoredcnt(0))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(7)));
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</td></tr><tr><td>
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FDCPE_LED4: FDCPE port map (LED(4),LED_D(4),XSTALIN,'0','0');
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<br/> LED_D(4) <= ((NOT LED(6) AND LED(4) AND NOT HZIN)
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND LED(5) AND alreadystoredcnt(0))
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<br/> OR (LED(6) AND LED(5) AND NOT HZIN)
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<br/> OR (NOT LED(6) AND LED(4) AND alreadystoredcnt(0))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(8)));
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</td></tr><tr><td>
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FDCPE_LED5: FDCPE port map (LED(5),LED_D(5),XSTALIN,'0','0');
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<br/> LED_D(5) <= ((NOT LED(6) AND LED(5) AND NOT HZIN)
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(13))
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<br/> OR (LED(6) AND storecounta(13) AND NOT HZIN)
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<br/> OR (NOT LED(6) AND LED(5) AND alreadystoredcnt(0))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(9)));
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</td></tr><tr><td>
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FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),XSTALIN,'0','0');
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<br/> LED_T(6) <= ((NOT LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND NOT uartskip(0))
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<br/> OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
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<br/> uartctr(3) AND uartctr(4))
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<br/> OR (LED(6) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
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<br/> uartskip(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
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<br/> uartctr(3) AND uartctr(4))
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<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
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<br/> uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
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<br/> uartctr(4) AND NOT HZIN));
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</td></tr><tr><td>
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FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),XSTALIN,'0','0');
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<br/> LED_T(7) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
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<br/> uartctr(2) AND uartctr(3) AND uartctr(4))
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<br/> OR (NOT LED(7) AND LED(6) AND NOT alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
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<br/> uartctr(3) AND uartctr(4) AND NOT HZIN));
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</td></tr><tr><td>
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FDCPE_TX: FDCPE port map (TX,TX_D,XSTALIN,'0','0');
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<br/> TX_D <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND NOT resetclk(0) AND storecounta(1))
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<br/> OR (NOT LED(6) AND NOT resetclk(0) AND TX)
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<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(1) AND
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<br/> HZIN)
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<br/> OR (NOT LED(6) AND NOT alreadystoredcnt(0) AND HZIN AND TX));
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</td></tr><tr><td>
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FDCPE_alreadystoredcnt0: FDCPE port map (alreadystoredcnt(0),alreadystoredcnt_D(0),XSTALIN,'0','0');
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<br/> alreadystoredcnt_D(0) <= ((LED(7) AND NOT LED(6) AND NOT resetclk(0) AND uartskip(0) AND
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<br/> NOT HZIN)
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<br/> OR (NOT alreadystoredcnt(0) AND NOT HZIN));
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</td></tr><tr><td>
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FDCPE_clkcounta0: FDCPE port map (clkcounta(0),clkcounta_D(0),XSTALIN,'0','0');
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<br/> clkcounta_D(0) <= ((NOT resetclk(0) AND NOT clkcounta(0))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND NOT clkcounta(0)));
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</td></tr><tr><td>
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FDCPE_clkcounta1: FDCPE port map (clkcounta(1),clkcounta_D(1),XSTALIN,'0','0');
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<br/> clkcounta_D(1) <= ((NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> NOT clkcounta(1))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND NOT clkcounta(0) AND
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<br/> clkcounta(1))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND NOT clkcounta(1))
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<br/> OR (NOT resetclk(0) AND NOT clkcounta(0) AND clkcounta(1)));
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</td></tr><tr><td>
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FTCPE_clkcounta2: FTCPE port map (clkcounta(2),clkcounta_T(2),XSTALIN,'0','0');
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<br/> clkcounta_T(2) <= ((NOT resetclk(0) AND clkcounta(0) AND clkcounta(1))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1))
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<br/> OR (alreadystoredcnt(0) AND resetclk(0) AND clkcounta(2))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(2)));
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</td></tr><tr><td>
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FTCPE_clkcounta3: FTCPE port map (clkcounta(3),clkcounta_T(3),XSTALIN,'0','0');
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<br/> clkcounta_T(3) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(3))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(3))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2)));
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</td></tr><tr><td>
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FTCPE_clkcounta4: FTCPE port map (clkcounta(4),clkcounta_T(4),XSTALIN,'0','0');
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<br/> clkcounta_T(4) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(4))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(4))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3)));
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</td></tr><tr><td>
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FTCPE_clkcounta5: FTCPE port map (clkcounta(5),clkcounta_T(5),XSTALIN,'0','0');
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<br/> clkcounta_T(5) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(5))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(5))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3) AND clkcounta(4))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4)));
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</td></tr><tr><td>
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FTCPE_clkcounta6: FTCPE port map (clkcounta(6),clkcounta_T(6),XSTALIN,'0','0');
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<br/> clkcounta_T(6) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(6))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(6))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
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<br/> clkcounta(5)));
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</td></tr><tr><td>
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FTCPE_clkcounta7: FTCPE port map (clkcounta(7),clkcounta_T(7),XSTALIN,'0','0');
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<br/> clkcounta_T(7) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(7))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(7))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
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<br/> clkcounta(6))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
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<br/> clkcounta(5) AND clkcounta(6)));
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</td></tr><tr><td>
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FTCPE_clkcounta8: FTCPE port map (clkcounta(8),clkcounta_T(8),XSTALIN,'0','0');
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<br/> clkcounta_T(8) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(8))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(8))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
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<br/> clkcounta(6) AND clkcounta(7))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
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<br/> clkcounta(5) AND clkcounta(6) AND clkcounta(7)));
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</td></tr><tr><td>
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FTCPE_clkcounta9: FTCPE port map (clkcounta(9),clkcounta_T(9),XSTALIN,'0','0');
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<br/> clkcounta_T(9) <= ((alreadystoredcnt(0) AND resetclk(0) AND clkcounta(9))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(9))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
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<br/> clkcounta(6) AND clkcounta(7) AND clkcounta(8))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
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<br/> clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8)));
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</td></tr><tr><td>
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FTCPE_clkcounta10: FTCPE port map (clkcounta(10),clkcounta_T(10),XSTALIN,'0','0');
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<br/> clkcounta_T(10) <= ((alreadystoredcnt(0) AND resetclk(0) AND
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<br/> clkcounta(10))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(10))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(1) AND
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<br/> clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
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<br/> clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
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<br/> clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
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<br/> clkcounta(9)));
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</td></tr><tr><td>
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FTCPE_clkcounta11: FTCPE port map (clkcounta(11),clkcounta_T(11),XSTALIN,'0','0');
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<br/> clkcounta_T(11) <= ((alreadystoredcnt(0) AND resetclk(0) AND
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<br/> clkcounta(11))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(11))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(10) AND
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<br/> clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
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<br/> clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
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<br/> clkcounta(9))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(10) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
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<br/> clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
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<br/> clkcounta(8) AND clkcounta(9)));
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</td></tr><tr><td>
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FTCPE_clkcounta12: FTCPE port map (clkcounta(12),clkcounta_T(12),XSTALIN,'0','0');
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<br/> clkcounta_T(12) <= ((alreadystoredcnt(0) AND resetclk(0) AND
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<br/> clkcounta(12))
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<br/> OR (resetclk(0) AND NOT HZIN AND clkcounta(12))
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<br/> OR (NOT resetclk(0) AND clkcounta(0) AND clkcounta(10) AND
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<br/> clkcounta(11) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
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<br/> clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
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<br/> clkcounta(8) AND clkcounta(9))
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0) AND
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<br/> clkcounta(10) AND clkcounta(11) AND clkcounta(1) AND clkcounta(2) AND
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<br/> clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
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<br/> clkcounta(7) AND clkcounta(8) AND clkcounta(9)));
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</td></tr><tr><td>
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FDCPE_resetclk0: FDCPE port map (resetclk(0),resetclk_D(0),XSTALIN,'0','0');
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<br/> resetclk_D(0) <= (NOT alreadystoredcnt(0) AND HZIN);
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</td></tr><tr><td>
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FDCPE_storecounta1: FDCPE port map (storecounta(1),storecounta_D(1),XSTALIN,'0','0');
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<br/> storecounta_D(1) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND NOT resetclk(0) AND storecounta(2))
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<br/> OR (NOT LED(6) AND NOT resetclk(0) AND storecounta(1))
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<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(2) AND
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<br/> HZIN)
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<br/> OR (NOT LED(6) AND NOT alreadystoredcnt(0) AND storecounta(1) AND
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<br/> HZIN));
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</td></tr><tr><td>
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FDCPE_storecounta2: FDCPE port map (storecounta(2),storecounta_D(2),XSTALIN,'0','0');
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<br/> storecounta_D(2) <= ((NOT LED(6) AND storecounta(2))
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND storecounta(3))
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<br/> OR (alreadystoredcnt(0) AND resetclk(0))
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<br/> OR (resetclk(0) AND NOT HZIN));
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</td></tr><tr><td>
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FDCPE_storecounta3: FDCPE port map (storecounta(3),storecounta_D(3),XSTALIN,'0','0');
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<br/> storecounta_D(3) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(3))
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<br/> OR (NOT LED(6) AND storecounta(3) AND NOT HZIN)
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
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<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
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<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(4))
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<br/> OR (LED(6) AND storecounta(4) AND NOT HZIN)
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<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(0)));
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</td></tr><tr><td>
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FDCPE_storecounta4: FDCPE port map (storecounta(4),storecounta_D(4),XSTALIN,'0','0');
|
|
<br/> storecounta_D(4) <= ((NOT LED(6) AND storecounta(4) AND NOT HZIN)
|
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<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(5))
|
|
<br/> OR (LED(6) AND storecounta(5) AND NOT HZIN)
|
|
<br/> OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(4))
|
|
<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(1)));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta5: FDCPE port map (storecounta(5),storecounta_D(5),XSTALIN,'0','0');
|
|
<br/> storecounta_D(5) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(5))
|
|
<br/> OR (NOT LED(6) AND storecounta(5) AND NOT HZIN)
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(6))
|
|
<br/> OR (LED(6) AND storecounta(6) AND NOT HZIN)
|
|
<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(2)));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta6: FDCPE port map (storecounta(6),storecounta_D(6),XSTALIN,'0','0');
|
|
<br/> storecounta_D(6) <= ((NOT LED(6) AND storecounta(6) AND NOT HZIN)
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND LED(0) AND alreadystoredcnt(0))
|
|
<br/> OR (LED(6) AND LED(0) AND NOT HZIN)
|
|
<br/> OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(6))
|
|
<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(3)));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta13: FDCPE port map (storecounta(13),storecounta_D(13),XSTALIN,'0','0');
|
|
<br/> storecounta_D(13) <= ((NOT LED(6) AND storecounta(13) AND NOT HZIN)
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(14))
|
|
<br/> OR (LED(6) AND storecounta(14) AND NOT HZIN)
|
|
<br/> OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(13))
|
|
<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(10)));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta14: FDCPE port map (storecounta(14),storecounta_D(14),XSTALIN,'0','0');
|
|
<br/> storecounta_D(14) <= ((NOT LED(6) AND alreadystoredcnt(0) AND storecounta(14))
|
|
<br/> OR (NOT LED(6) AND storecounta(14) AND NOT HZIN)
|
|
<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(11))
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(15))
|
|
<br/> OR (LED(6) AND storecounta(15) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta15: FDCPE port map (storecounta(15),storecounta_D(15),XSTALIN,'0','0');
|
|
<br/> storecounta_D(15) <= ((NOT LED(6) AND storecounta(15) AND NOT HZIN)
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND alreadystoredcnt(0) AND storecounta(16))
|
|
<br/> OR (LED(6) AND storecounta(16) AND NOT HZIN)
|
|
<br/> OR (NOT LED(6) AND alreadystoredcnt(0) AND storecounta(15))
|
|
<br/> OR (NOT alreadystoredcnt(0) AND HZIN AND clkcounta(12)));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta16: FDCPE port map (storecounta(16),storecounta_D(16),XSTALIN,'0','0');
|
|
<br/> storecounta_D(16) <= ((LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND storecounta(17))
|
|
<br/> OR (NOT LED(6) AND storecounta(16))
|
|
<br/> OR (alreadystoredcnt(0) AND resetclk(0))
|
|
<br/> OR (resetclk(0) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta17: FDCPE port map (storecounta(17),storecounta_D(17),XSTALIN,'0','0');
|
|
<br/> storecounta_D(17) <= ((NOT LED(6) AND NOT alreadystoredcnt(0) AND storecounta(17) AND
|
|
<br/> HZIN)
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND NOT resetclk(0) AND storecounta(18))
|
|
<br/> OR (NOT LED(6) AND NOT resetclk(0) AND storecounta(17))
|
|
<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND storecounta(18) AND
|
|
<br/> HZIN));
|
|
</td></tr><tr><td>
|
|
FDCPE_storecounta18: FDCPE port map (storecounta(18),storecounta_D(18),XSTALIN,'0','0');
|
|
<br/> storecounta_D(18) <= ((LED(6) AND NOT alreadystoredcnt(0) AND HZIN)
|
|
<br/> OR (NOT alreadystoredcnt(0) AND storecounta(18) AND HZIN)
|
|
<br/> OR (LED(7) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> uartskip(0) AND NOT HZIN)
|
|
<br/> OR (LED(6) AND NOT resetclk(0))
|
|
<br/> OR (NOT resetclk(0) AND storecounta(18)));
|
|
</td></tr><tr><td>
|
|
FTCPE_uartctr0: FTCPE port map (uartctr(0),uartctr_T(0),XSTALIN,'0','0');
|
|
<br/> uartctr_T(0) <= ((LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
<br/> uartctr(3) AND uartctr(4))
|
|
<br/> OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0))
|
|
<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
<br/> uartctr(4) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FTCPE_uartctr1: FTCPE port map (uartctr(1),uartctr_T(1),XSTALIN,'0','0');
|
|
<br/> uartctr_T(1) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND uartctr(0))
|
|
<br/> OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
<br/> uartctr(3) AND uartctr(4))
|
|
<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
<br/> uartctr(4) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FTCPE_uartctr2: FTCPE port map (uartctr(2),uartctr_T(2),XSTALIN,'0','0');
|
|
<br/> uartctr_T(2) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1))
|
|
<br/> OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
<br/> uartctr(3) AND uartctr(4))
|
|
<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
<br/> uartctr(4) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FTCPE_uartctr3: FTCPE port map (uartctr(3),uartctr_T(3),XSTALIN,'0','0');
|
|
<br/> uartctr_T(3) <= ((NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
|
|
<br/> uartctr(2))
|
|
<br/> OR (LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
<br/> uartctr(3) AND uartctr(4))
|
|
<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
<br/> uartctr(4) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FTCPE_uartctr4: FTCPE port map (uartctr(4),uartctr_T(4),XSTALIN,'0','0');
|
|
<br/> uartctr_T(4) <= ((LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartctr(0) AND uartctr(1) AND uartctr(2) AND
|
|
<br/> uartctr(3) AND uartctr(4))
|
|
<br/> OR (NOT LED(7) AND LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND uartctr(0) AND uartctr(1) AND
|
|
<br/> uartctr(2) AND uartctr(3))
|
|
<br/> OR (LED(6) AND NOT alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> uartctr(0) AND uartctr(1) AND uartctr(2) AND uartctr(3) AND
|
|
<br/> uartctr(4) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
FTCPE_uartskip0: FTCPE port map (uartskip(0),uartskip_T(0),XSTALIN,'0','0');
|
|
<br/> uartskip_T(0) <= ((NOT LED(7) AND alreadystoredcnt(0) AND NOT resetclk(0) AND
|
|
<br/> NOT uartskip(0))
|
|
<br/> OR (LED(7) AND NOT LED(6) AND alreadystoredcnt(0) AND
|
|
<br/> NOT resetclk(0) AND uartskip(0) AND NOT HZIN));
|
|
</td></tr><tr><td>
|
|
Register Legend:
|
|
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
|
|
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
|
|
<br/> LDCP (Q,D,G,CLR,PRE);
|
|
</td></tr><tr><td>
|
|
</td></tr>
|
|
</table>
|
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