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259 lines
9.9 KiB
259 lines
9.9 KiB
Release 14.7 - xst P.20131013 (lin)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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-->
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Reading design: counta.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "counta.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "counta"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : counta
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.vhd" in Library work.
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Entity <counta> compiled.
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Entity <counta> (Architecture <behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <counta> in library <work> (architecture <behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <counta> in library <work> (Architecture <behavioral>).
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Entity <counta> analyzed. Unit <counta> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <counta>.
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Related source file is "/home/dev/Desktop/code/xilinx/file/cpld_countertest9/counta.vhd".
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WARNING:Xst:1780 - Signal <ORvalforstore> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found 1-bit register for signal <alreadystoredcnt<0>>.
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Found 13-bit up counter for signal <clkcounta>.
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Found 1-bit register for signal <resetclk<0>>.
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Found 19-bit register for signal <storecounta>.
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Found 5-bit up counter for signal <uartctr>.
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Found 1-bit register for signal <uartnow<0>>.
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Found 1-bit register for signal <uartskip<0>>.
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Found 1-bit register for signal <waitnow<0>>.
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Summary:
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inferred 2 Counter(s).
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inferred 22 D-type flip-flop(s).
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Unit <counta> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 2
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13-bit up counter : 1
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5-bit up counter : 1
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# Registers : 24
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1-bit register : 24
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Counters : 2
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13-bit up counter : 1
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5-bit up counter : 1
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# Registers : 22
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Flip-Flops : 22
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <counta> ...
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implementation constraint: INIT=r : storecounta_10
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implementation constraint: INIT=r : storecounta_0
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implementation constraint: INIT=r : waitnow_0
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implementation constraint: INIT=r : storecounta_11
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implementation constraint: INIT=r : storecounta_1
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implementation constraint: INIT=r : storecounta_12
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implementation constraint: INIT=r : storecounta_2
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implementation constraint: INIT=r : storecounta_13
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implementation constraint: INIT=r : storecounta_3
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implementation constraint: INIT=r : storecounta_14
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implementation constraint: INIT=r : storecounta_4
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implementation constraint: INIT=r : storecounta_15
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implementation constraint: INIT=r : storecounta_5
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implementation constraint: INIT=r : storecounta_16
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implementation constraint: INIT=r : storecounta_6
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implementation constraint: INIT=r : storecounta_17
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implementation constraint: INIT=r : storecounta_7
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implementation constraint: INIT=r : storecounta_18
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implementation constraint: INIT=r : storecounta_8
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implementation constraint: INIT=r : storecounta_9
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implementation constraint: INIT=r : uartnow_0
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implementation constraint: INIT=r : uartskip_0
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implementation constraint: INIT=r : alreadystoredcnt_0
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implementation constraint: INIT=r : uartctr_2
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implementation constraint: INIT=r : resetclk_0
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implementation constraint: INIT=r : clkcounta_12
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implementation constraint: INIT=r : uartctr_3
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implementation constraint: INIT=r : clkcounta_0
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implementation constraint: INIT=r : clkcounta_1
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implementation constraint: INIT=r : clkcounta_2
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implementation constraint: INIT=r : clkcounta_3
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implementation constraint: INIT=r : clkcounta_4
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implementation constraint: INIT=r : clkcounta_5
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implementation constraint: INIT=r : clkcounta_6
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implementation constraint: INIT=r : clkcounta_7
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implementation constraint: INIT=r : clkcounta_8
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implementation constraint: INIT=r : clkcounta_9
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implementation constraint: INIT=r : clkcounta_10
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implementation constraint: INIT=r : clkcounta_11
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implementation constraint: INIT=r : uartctr_4
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implementation constraint: INIT=r : uartctr_0
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implementation constraint: INIT=r : uartctr_1
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : counta.ngr
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Top Level Output File Name : counta
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : Yes
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Target Technology : XC9500XL CPLDs
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Macro Preserve : YES
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XOR Preserve : YES
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Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 11
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Cell Usage :
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# BELS : 395
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# AND2 : 131
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# AND3 : 30
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# AND4 : 13
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# AND5 : 1
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# GND : 1
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# INV : 156
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# OR2 : 45
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# OR3 : 1
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# OR4 : 1
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# XOR2 : 16
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# FlipFlops/Latches : 42
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# FD : 13
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# FDCE : 29
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# IO Buffers : 11
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# IBUF : 2
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# OBUF : 9
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=========================================================================
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Total REAL time to Xst completion: 10.00 secs
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Total CPU time to Xst completion: 10.28 secs
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-->
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Total memory usage is 165256 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 1 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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