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<h1 id="firstHeading" class="firstHeading">CPLD: Complex programmable logic devices</h1>
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<h3 id="siteSub">From DP</h3>
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<table style="width: 30em; font-size: 11px; border: 1px solid #bbb; background-color: #eee; color: #444; padding: 0.2em; margin-bottom: 0.5em; margin-left: 1em; float: right; clear: right; text-align:left;">
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<tr>
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<th style="text-align: center; color: #fff; border: 1px solid #1E7B8E; background-color:#1E7B8E; font-size: 11px;" colspan="2">Project Summary
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</th></tr>
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<tr>
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<td colspan="2">
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</td></tr>
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<tr>
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<th> Name:
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</th><td> CPLD: Complex programmable logic devices
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</td></tr>
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<tr>
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<th> Buy it:
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</th><td> <a href="http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html?cPath=174" class="external text" rel="nofollow">Get one for $15 at Seeed Studio</a>
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</td></tr>
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<tr>
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<th> Price:
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</th><td> $15
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</td></tr>
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<tr>
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<th> Status:
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</th><td> <a href="/docs/Project_status#Development_status" title="Project status">Mature</a>
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</td></tr>
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<tr>
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<th> Manufacturing:
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</th><td> <a href="/docs/Project_status#Manufacturing" title="Project status">Shipping</a>
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</td></tr>
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<tr>
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<th> Forum:
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</th><td> <a href="http://dangerousprototypes.com/forum/viewforum.php?f=51" class="external text" rel="nofollow">CPLD: Complex programmable logic devices Forum</a>
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</td></tr></table><a href="/docs/File:Xc9572-cpld-breakoutvib.jpg" class="image"><img alt="Xc9572-cpld-breakoutvib.jpg" src="/docs/images/6/6c/Xc9572-cpld-breakoutvib.jpg" width="490" height="277" /></a>
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<p>Ever get stuck choosing the right logic chip combination or voltage level translator? Give up the hunt and create your own custom logic chip. CPLDs can give you the logic you need, with the pinout you want, while saving board space and board revisions.
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</p><p>Development boards from Dangerous Prototypes will help you build your first custom logic chip using simple schematic entry, Verilog, or VHDL.
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</p>
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<ul><li>XC9572XL or XC2C64A CPLDs
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</li><li>On-board power supply for core and pins
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</li><li>Selectable 3.3volt or external supply for pins (1.8volt to 3.3volt)
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</li><li>LEDs for output, push button for input
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</li><li>Easy to program with the Bus Pirate
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</li><li>Open source (CC-BY-SA)
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</li></ul>
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<p><b><a href="http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html" class="external text" rel="nofollow">CoolRunner-II</a> and <a href="http://www.seeedstudio.com/depot/xc9572xl-cpld-development-board-p-799.html" class="external text" rel="nofollow">XC9572XL</a> versions available for $15.</b>
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</p>
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<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
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<ul>
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<li class="toclevel-1 tocsection-1"><a href="#Downloads"><span class="tocnumber">1</span> <span class="toctext">Downloads</span></a></li>
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<li class="toclevel-1 tocsection-2"><a href="#Hardware"><span class="tocnumber">2</span> <span class="toctext">Hardware</span></a>
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<ul>
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<li class="toclevel-2 tocsection-3"><a href="#XC9500XL"><span class="tocnumber">2.1</span> <span class="toctext">XC9500XL</span></a></li>
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<li class="toclevel-2 tocsection-4"><a href="#CoolRunnerII"><span class="tocnumber">2.2</span> <span class="toctext">CoolRunnerII</span></a></li>
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</ul>
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</li>
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<li class="toclevel-1 tocsection-5"><a href="#CPLD_development_tutorials"><span class="tocnumber">3</span> <span class="toctext">CPLD development tutorials</span></a>
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<ul>
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<li class="toclevel-2 tocsection-6"><a href="#Schematic_entry"><span class="tocnumber">3.1</span> <span class="toctext">Schematic entry</span></a></li>
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<li class="toclevel-2 tocsection-7"><a href="#Verilog"><span class="tocnumber">3.2</span> <span class="toctext">Verilog</span></a></li>
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<li class="toclevel-2 tocsection-8"><a href="#VHDL"><span class="tocnumber">3.3</span> <span class="toctext">VHDL</span></a></li>
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<li class="toclevel-2 tocsection-9"><a href="#Plunify"><span class="tocnumber">3.4</span> <span class="toctext">Plunify</span></a></li>
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<li class="toclevel-2 tocsection-10"><a href="#ISE_Webpack"><span class="tocnumber">3.5</span> <span class="toctext">ISE Webpack</span></a></li>
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</ul>
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</li>
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<li class="toclevel-1 tocsection-11"><a href="#Example_devices"><span class="tocnumber">4</span> <span class="toctext">Example devices</span></a>
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<ul>
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<li class="toclevel-2 tocsection-12"><a href="#Schematic"><span class="tocnumber">4.1</span> <span class="toctext">Schematic</span></a></li>
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<li class="toclevel-2 tocsection-13"><a href="#VHDL_2"><span class="tocnumber">4.2</span> <span class="toctext">VHDL</span></a></li>
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<li class="toclevel-2 tocsection-14"><a href="#Verilog_2"><span class="tocnumber">4.3</span> <span class="toctext">Verilog</span></a></li>
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</ul>
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</li>
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<li class="toclevel-1 tocsection-15"><a href="#Programming"><span class="tocnumber">5</span> <span class="toctext">Programming</span></a>
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<ul>
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<li class="toclevel-2 tocsection-16"><a href="#Additional_methods"><span class="tocnumber">5.1</span> <span class="toctext">Additional methods</span></a></li>
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</ul>
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</li>
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<li class="toclevel-1 tocsection-17"><a href="#Links"><span class="tocnumber">6</span> <span class="toctext">Links</span></a>
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<ul>
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<li class="toclevel-2 tocsection-18"><a href="#Verilog_3"><span class="tocnumber">6.1</span> <span class="toctext">Verilog</span></a></li>
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</ul>
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</li>
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<li class="toclevel-1 tocsection-19"><a href="#Resources"><span class="tocnumber">7</span> <span class="toctext">Resources</span></a></li>
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<li class="toclevel-1 tocsection-20"><a href="#License"><span class="tocnumber">8</span> <span class="toctext">License</span></a></li>
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</ul>
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</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
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<h2> <span class="mw-headline" id="Downloads">Downloads</span></h2>
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<ul><li><a href="https://github.com/DangerousPrototypes/Downloads/blob/master/CPLD.Breakout.Package.v1.0.zip" class="external text" rel="nofollow">Download CPLD Breakout Package</a>
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</li><li><a href="https://github.com/DangerousPrototypes/CPLD_Breakout" class="external text" rel="nofollow">Browse the project's GitHub</a>
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</li></ul>
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<h2> <span class="mw-headline" id="Hardware">Hardware</span></h2>
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<ul><li><a href="/docs/Xilinx_CPLDs:_XC9500_vs_CoolRunner-II" title="Xilinx CPLDs: XC9500 vs CoolRunner-II">Xilinx CPLDs: XC9500 vs CoolRunner-II</a>
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</li></ul>
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<h3> <span class="mw-headline" id="XC9500XL">XC9500XL</span></h3>
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<p><a href="/docs/File:Xc9572-cpld-breakoutvib.jpg" class="image"><img alt="Xc9572-cpld-breakoutvib.jpg" src="/docs/images/thumb/6/6c/Xc9572-cpld-breakoutvib.jpg/150px-Xc9572-cpld-breakoutvib.jpg" width="150" height="85" /></a>
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</p><p>The Xilinx XC9500XL family has some of the cheapest and readily available CPLDs out there. Inputs are 5volt tolerant and they can be run from a single 3.3volt supply.
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</p>
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<ul><li><a href="/docs/XC9500XL_CPLD_breakout_board" title="XC9500XL CPLD breakout board">XC9500XL CPLD development board</a> hardware design
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</li><li><a href="/docs/XC9572XL_CPLD_dev-board_introduction" title="XC9572XL CPLD dev-board introduction">XC9572XL CPLD dev-board introduction</a>
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</li><li><a href="/docs/Xilinx_XC9500XL_CPLD_quick_start" title="Xilinx XC9500XL CPLD quick start">XC9500XL CPLD quick start</a>
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</li><li><a href="/docs/XC9572XL_dev-board_v1_errors" title="XC9572XL dev-board v1 errors">XC9572XL dev-board v1 errors</a>
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</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds054.pdf" class="external text" rel="nofollow">XC9500XL family manual</a>
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</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds057.pdf" class="external text" rel="nofollow">XC9572XL device datasheet</a>
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</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds058.pdf" class="external text" rel="nofollow">XC9536XL device datasheet</a> (smaller version of XC9572XL)
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</li></ul>
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<h3> <span class="mw-headline" id="CoolRunnerII">CoolRunnerII</span></h3>
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<p><a href="/docs/File:Xc2c64a_cpld_breakout-vib.jpg" class="image"><img alt="Xc2c64a cpld breakout-vib.jpg" src="/docs/images/thumb/7/70/Xc2c64a_cpld_breakout-vib.jpg/150px-Xc2c64a_cpld_breakout-vib.jpg" width="150" height="84" /></a>
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</p><p>The CoolRunner-II family is newer than the XC9500XL, and has a few extra features like multiple IO voltage banks for voltage translation, internal pull-up resistors and pin keepers and a clock divider. Requires a 1.8volt core supply and a 1.2-3.3volt IO pin supply.
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</p>
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<ul><li><a href="/docs/CoolRunner-II_CPLD_breakout_board" title="CoolRunner-II CPLD breakout board">CoolRunner-II CPLD development board</a> hardware design
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</li><li><a href="/docs/XC2C64A_CPLD_dev-board_introduction" title="XC2C64A CPLD dev-board introduction">XC2C64A CPLD dev-board introduction</a>
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</li><li><a href="/docs/Xilinx_CoolRunner-II_CPLD_quick_start" title="Xilinx CoolRunner-II CPLD quick start">CoolRunner-II CPLD quick start</a>
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</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf" class="external text" rel="nofollow">CoolRunner-II family manual</a>
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</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds311.pdf" class="external text" rel="nofollow">XC2C64A device datasheet</a>
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</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds310.pdf" class="external text" rel="nofollow">XC2C32A device datasheet</a> (smaller version of XC2C64A used on Bus Blaster v2)
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</li></ul>
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<h2> <span class="mw-headline" id="CPLD_development_tutorials">CPLD development tutorials</span></h2>
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<p>This tutorial shows how to use simple schematics to design the logic in a Xilinx CoolRunner-II or XC9500 CPLD.
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</p>
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<ul><li><a href="http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html" class="external text" rel="nofollow">Free Xilinx ISE Webpack download</a>
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</li></ul>
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<p>Tutorial files:
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</p>
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<ul><li>See <a href="https://github.com/DangerousPrototypes/Downloads/blob/master/CPLDdev.package.v1.1.zip" class="external text" rel="nofollow">CPLDdev.package.v1.1.zip</a>
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</li></ul>
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<p>The Bus Pirate XSVF player and a .bat file are included with every example. Modify the COM post and click to load.
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</p>
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<h3> <span class="mw-headline" id="Schematic_entry">Schematic entry</span></h3>
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<ul><li><a href="/docs/CPLD_intro_1:_Light_a_LED" title="CPLD intro 1: Light a LED">CPLD intro 1: Light a LED</a>
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</li><li><a href="/docs/CPLD_intro_2:_Toggle_a_LED_with_a_button" title="CPLD intro 2: Toggle a LED with a button">CPLD intro 2: Toggle a LED with a button</a>
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</li><li><a href="/docs/CPLD_intro_3:_Inverse_LED_toggle" title="CPLD intro 3: Inverse LED toggle">CPLD intro 3: Inverse LED toggle</a>
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</li></ul>
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<h3> <span class="mw-headline" id="Verilog">Verilog</span></h3>
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<ul><li><a href="/docs/CPLD_Verilog_intro_1:_Light_a_LED" title="CPLD Verilog intro 1: Light a LED">CPLD Verilog intro 1: Light a LED</a>
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</li><li><a href="/docs/CPLD_Verilog_intro_2:_Toggle_a_LED_with_a_button" title="CPLD Verilog intro 2: Toggle a LED with a button">CPLD Verilog intro 2: Toggle a LED with a button</a>
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</li><li><a href="/docs/CPLD_Verilog_intro_3:_Inverse_LED_toggle" title="CPLD Verilog intro 3: Inverse LED toggle">CPLD Verilog intro 3: Inverse LED toggle</a>
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</li></ul>
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<h3> <span class="mw-headline" id="VHDL">VHDL</span></h3>
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<ul><li><a href="/docs/CPLD_VHDL_intro_1:_Light_a_LED" title="CPLD VHDL intro 1: Light a LED">CPLD VHDL intro 1: Light a LED</a>
|
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</li><li><a href="/docs/CPLD_VHDL_intro_2:_Toggle_a_LED_with_a_button" title="CPLD VHDL intro 2: Toggle a LED with a button">CPLD VHDL intro 2: Toggle a LED with a button</a>
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</li><li><a href="/docs/CPLD_VHDL_intro_3:_Inverse_LED_toggle" title="CPLD VHDL intro 3: Inverse LED toggle">CPLD VHDL intro 3: Inverse LED toggle</a>
|
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</li><li><a href="/docs/CPLD_intro_4:_replacing_simple_logic_vhdl" title="CPLD intro 4: replacing simple logic vhdl">CPLD VHDL intro 4: Replacing simple logic</a>
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</li></ul>
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<h3> <span class="mw-headline" id="Plunify">Plunify</span></h3>
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<p><a href="http://www.plunify.com" class="external text" rel="nofollow">Plunify</a> is a cloud-based compiler for <s>Xilinx</s> and Altera chips. <s>The CPLD examples are already loaded, all you have to do is sign up for a free account and copy the tutorial from the <i>add IP</i> tab.</s> Unfortunately it no longer supports Xilinx chips.
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</p>
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<ul><li><a href="http://www.youtube.com/watch?v=WWFyVMZUMRE" class="external text" rel="nofollow">How-to video: use Plunify with the CPLD examples</a>
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</li><li><a href="/docs/Plunify_online_compiler_overview" title="Plunify online compiler overview">Plunify online compiler overview</a>
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</li></ul>
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<h3> <span class="mw-headline" id="ISE_Webpack">ISE Webpack</span></h3>
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<ul><li><a href="/docs/Export_(X)SVF_from_Xilinx_ISE_Webpack" title="Export (X)SVF from Xilinx ISE Webpack">Export (X)SVF from Xilinx ISE Webpack</a>
|
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</li><li><a href="/docs/CPLD:_simulate_designs" title="CPLD: simulate designs">CPLD: simulate designs</a>
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</li><li><a href="/docs/Enable_CoolRunner-II_CPLD_pull-up_resistors" title="Enable CoolRunner-II CPLD pull-up resistors">Enable CoolRunner-II CPLD pull-up resistors</a>
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</li></ul>
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<h2> <span class="mw-headline" id="Example_devices">Example devices</span></h2>
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<ul><li><a href="https://github.com/DangerousPrototypes/Downloads/blob/master/CPLDdev.package.v1.1.zip" class="external text" rel="nofollow">CPLDdev.package.v1.1.zip</a>
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</li><li><a href="https://github.com/DangerousPrototypes/CPLD_Breakout/tree/master/package/Device_examples" class="external text" rel="nofollow">Latest in SVN</a>
|
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</li></ul>
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<h3> <span class="mw-headline" id="Schematic">Schematic</span></h3>
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<ul><li><a href="/docs/CPLD_example:_Dual_74xx595s" title="CPLD example: Dual 74xx595s">CPLD example: Dual 74xx595s</a>
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</li><li><a href="/docs/CPLD_example:_Dual_latch" title="CPLD example: Dual latch">CPLD example: Dual latch</a>
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</li><li><a href="/docs/CPLD_example:_FIFO" title="CPLD example: FIFO">CPLD example: FIFO</a>
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</li><li><a href="/docs/CPLD_example:_Motor_Phase_Interlock" title="CPLD example: Motor Phase Interlock">CPLD example: Motor Phase Interlock</a>
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</li><li><a href="/docs/CPLD_example:_Priority_Decoder" title="CPLD example: Priority Decoder">CPLD example: Priority Decoder</a>
|
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</li><li><a href="/docs/CPLD_example:_PWM_Generator" title="CPLD example: PWM Generator">CPLD example: PWM Generator</a>
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</li><li><a href="/docs/CPLD_example:_Addressable_Latch" title="CPLD example: Addressable Latch">CPLD example: Addressable Latch</a>
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</li></ul>
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<h3> <span class="mw-headline" id="VHDL_2">VHDL</span></h3>
|
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<ul><li>Our <a href="/docs/7400_series_library_in_VHDL" title="7400 series library in VHDL">7400 series library in VHDL</a>
|
|
</li><li><a href="http://opencores.org/project,mcpu" class="external text" rel="nofollow">32 macrocell CPU</a> at OpenCores.org
|
|
</li><li><a href="/docs/CPLD_ring_oscillator" title="CPLD ring oscillator">CPLD ring oscillator</a> a clock source without a crystal
|
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</li></ul>
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<h3> <span class="mw-headline" id="Verilog_2">Verilog</span></h3>
|
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<ul><li><a href="/docs/Lulu:_Yet_another_logic_analyzer" title="Lulu: Yet another logic analyzer">Logic analyzer example in 72 macrocells</a>
|
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</li></ul>
|
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<h2> <span class="mw-headline" id="Programming">Programming</span></h2>
|
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<ul><li><a href="/docs/Bus_Pirate_JTAG_XSVF_player" title="Bus Pirate JTAG XSVF player">CPLD programming with Bus Pirate, XSVF loader, and XSVF files</a>
|
|
</li><li><a href="/docs/CPLD_programming_with_Bus_Blaster,_urJTAG,_and_SVF_files" title="CPLD programming with Bus Blaster, urJTAG, and SVF files">CPLD programming with Bus Blaster, urJTAG, and SVF files</a> (currently CoolRunner-II only)
|
|
</li><li><a href="/docs/JTAG_SVF_to_XSVF_file_converter" title="JTAG SVF to XSVF file converter">JTAG SVF to XSVF file converter</a>
|
|
</li></ul>
|
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<h3> <span class="mw-headline" id="Additional_methods">Additional methods</span></h3>
|
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<ul><li><a href="http://www.xilinx.com/itp/3_1i/pdf/docs/jtg/jtg.pdf" class="external text" rel="nofollow">Parallel cables with IMPACT</a>
|
|
</li><li><a href="http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf" class="external text" rel="nofollow">XSVF player for any microcontroller</a> (used in Bus Pirate XSVF player)
|
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</li><li><a href="http://www.clifford.at/libxsvf/" class="external text" rel="nofollow">lib(X)SVF</a>
|
|
</li><li><a href="http://rmdir.de/~michael/xilinx/" class="external text" rel="nofollow">FT2232 programmers and IMPACT with alternate driver</a>
|
|
</li></ul>
|
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<h2> <span class="mw-headline" id="Links">Links</span></h2>
|
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<h3> <span class="mw-headline" id="Verilog_3">Verilog</span></h3>
|
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<ul><li><a href="http://www.asic-world.com/verilog/synthesis.html" class="external text" rel="nofollow">Synthesis tutorial</a> (a favorite tutorial)
|
|
</li><li><a href="http://www.asic-world.com/tidbits/index.html" class="external text" rel="nofollow">Verilog concepts</a> (wire, reg, blocking, etc)
|
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</li></ul>
|
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<h2> <span class="mw-headline" id="Resources">Resources</span></h2>
|
|
<ul><li><a href="/docs/Xilinx_CPLD_breakout_development_scraps" title="Xilinx CPLD breakout development scraps">Xilinx CPLD breakout development scraps</a>
|
|
</li><li><a href="/docs/CPLD_development_board_manufacturing_resources" title="CPLD development board manufacturing resources">CPLD development board manufacturing resources</a>
|
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</li></ul>
|
|
<h2> <span class="mw-headline" id="License">License</span></h2>
|
|
<ul><li>Hardware: CC-BY-SA
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</li><li>CPLD demos projects: CC-0
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</li></ul>
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