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27 lines
537 B
27 lines
537 B
library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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entity counter is
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port (
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CLK_IN: in std_logic;
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RLED: out std_logic_vector(3 downto 0)
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);
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end counter ;
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architecture behav of counter is
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signal pres_count, next_count: std_logic_vector(24 downto 0);
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begin
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RLED <= pres_count(20 downto 17);
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sync_count: process(CLK_IN)
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begin
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if(rising_edge(CLK_IN)) then
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pres_count <= pres_count + 1;
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end if;
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end process sync_count;
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end architecture;
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