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73 lines
1.3 KiB

4 years ago
  1. ;
  2. ; tinyblink
  3. ; Blinks an LED on pin 4 (PB2)
  4. ;
  5. .DEVICE ATtiny10
  6. ; variables
  7. .EQU delayMult1 = 0xff ; the delay is delay3*delaymult2*delaymult1
  8. .EQU delayMult2 = 0xff
  9. .EQU delayMult3 = 0x0f
  10. .CSEG ; code section
  11. .ORG $0000 ; the starting address
  12. main:
  13. ; set up the stack
  14. ldi r16, high(RAMEND)
  15. out SPH, r16
  16. ldi r16, low(RAMEND)
  17. out SPL, r16
  18. ; set clock divider
  19. ldi r16, 0x00 ; clock divided by 1
  20. ldi r17, 0xD8 ; the key for CCP
  21. out CCP, r17 ; Configuration Change Protection, allows protected changes
  22. out CLKPSR, r16 ; sets the clock divider
  23. ; initialize port
  24. ldi r16, 1<<PB2 ; sets pin 4 (PB2) to putput
  25. out DDRB, r16 ; data direction
  26. ldi r16, 0x00 ; sets all pins low
  27. out PORTB, r16
  28. ; nop for sync
  29. nop
  30. loop:
  31. ; turn on and delay
  32. ldi r16, (1<<PB2)
  33. out PORTB, r16
  34. rcall delay
  35. ; turn off and delay
  36. ldi r16, 0x00
  37. out PORTB, r16
  38. rcall delay
  39. rjmp loop
  40. delay:
  41. ; not really needed, but keep r16-r18
  42. push r16
  43. push r17
  44. push r18
  45. ldi r16, delayMult1
  46. ldi r17, delayMult2
  47. ldi r18, delayMult3
  48. ; start delay loop
  49. delayLoop:
  50. subi r16, 1 ; subtract 1
  51. sbci r17, 0 ; if r16 was 0, subtract 1
  52. sbci r18, 0 ; if r17 was 0, subtract 1
  53. brne delayLoop ; while r18 is not 0, loop
  54. ; end delay loop
  55. pop r17
  56. pop r16
  57. pop r18
  58. ret