6

60hz_Divider/docs/12.tex

@@ -94,6 +94,9 @@ The schematics appear to be incorrect for the divide by 6 counter in the Practic
 As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
 
 
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an input clock (CMOS, not Quartz) of 1.536MHz. I then divided by 256 to get
+
 
 
 

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60hz_Divider/docs/14.tex

@@ -0,0 +1,105 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an input clock (CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. 
+
+
+
+\end{document}
+

60hz_Divider/docs/14.toc

@@ -0,0 +1,9 @@
+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{1}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{2}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{3}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{4}

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60hz_Divider/docs/15.tex

@@ -0,0 +1,105 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. The CPLD works with it, no problem.
+
+
+
+\end{document}
+

60hz_Divider/docs/15.tex~

@@ -0,0 +1,105 @@
+
+\documentclass[11pt]{article}
+%Gummi|065|=)
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage{xcolor}
+\usepackage[vcentering,dvips]{geometry}
+\geometry{papersize={6in,9in},total={4.5in,6.8in}}
+\title{\textbf{}}
+\author{Steak Electronics}
+\date{}
+\begin{document}
+
+%\maketitle
+
+\tableofcontents
+\textcolor{green!60!blue!70}{
+  \section{60Hz Divider}}
+
+
+\subsection{Overview}
+Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
+
+The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
+\begin{center}
+\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
+\captionof{figure}{60 Hz Logic Divider to 1Hz}
+\end{center}
+
+
+\subsection{Initial Notes: Counting the Hz}
+pseudo code goal:
+\begin{verbatim}
+Using 1Hz signal
+Start counting 1MHz every 1Hz
+when next cycle is received,
+   display count
+   start counting again
+\end{verbatim}
+That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
+
+ 4553 x 5 
+ 74hct132
+ 1MHz clock (or 6MHz clock), or some variation thereof
+ jk flip flop
+ 74376  - quad jk flip flop
+ 7476 - jk flip flop
+1mhz clk will be main counter,
+6 hz or 1 hz will be latch / reset
+
+I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
+
+\subsection{MAX7219 8 digit 7 LED segment Display Driver}
+Basic code tested with this was the LedControl arduino library.
+
+\begin{verbatim}
+/*
+ Now we need a LedControl to work with.
+ ***** These pin numbers will probably not work with your hardware *****
+ pin 12 is connected to the DataIn 
+ pin 11 is connected to the CLK 
+ pin 10 is connected to LOAD 
+ We have only a single MAX72XX.
+ */
+\end{verbatim}
+Some of the lines have to be edited to allow for all digits to be read, and
+also to lower intensity of display. I think also a component package (dark 
+grey clear plastic bag) in front of the leds with intensity 1 is about right.
+
+
+\subsection{CPLD Programming}
+Using the XC9500XL series. This chip has some limitations - which are good.
+
+As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
+
+\subsubsection{6KHz clock}
+Due to limitations of the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
+
+\subsubsection{UART output}
+I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
+
+However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
+
+
+\subsection{Divide by N Counters}
+
+\begin{center}
+\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
+\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
+\end{center}
+
+The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
+
+As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
+
+
+\subsection{Attiny 6KHz Clock}
+A small victory here: I setup an Attiny10 with an input clock oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
+6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
+to my other project using it. 
+
+
+
+\end{document}
+

60hz_Divider/docs/15.toc

@@ -0,0 +1,9 @@
+\contentsline {section}{\numberline {1}60Hz Divider}{1}
+\contentsline {subsection}{\numberline {1.1}Overview}{1}
+\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}
+\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}
+\contentsline {subsection}{\numberline {1.4}CPLD Programming}{3}
+\contentsline {subsubsection}{\numberline {1.4.1}6KHz clock}{3}
+\contentsline {subsubsection}{\numberline {1.4.2}UART output}{3}
+\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}
+\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{4}