@ -0,0 +1,17 @@ | |||
`default_nettype none | |||
// define a Blink module | |||
module Blink(input CLK_IN, output GLED5, output RLED1, output RLED2, output RLED3, output RLED4); | |||
// define a 24-bit counter to divide the clock down from 12MHz | |||
localparam WIDTH = 24; | |||
reg [WIDTH-1:0] counter; | |||
// run counter from 12MHz clock | |||
always @(posedge CLK_IN) | |||
counter <= counter + 1; | |||
// wire up the red LEDs to the counter MSB | |||
assign RLED1 = counter[WIDTH-1]; | |||
endmodule |
@ -0,0 +1,16 @@ | |||
#!/bin/bash | |||
#adapted from https://github.com/leedowthwaite/HelloIce | |||
#changes: separate folder for dev files | |||
#simplified bash script | |||
MAIN=$1 | |||
mkdir txtbin | |||
echo Using yosys to synthesize design | |||
yosys -p "synth_ice40 -blif txtbin/$MAIN.blif" $MAIN.v $@ | |||
echo Place and route with arachne-pnr | |||
arachne-pnr -d 1k -p icestick.pcf txtbin/$MAIN.blif -o txtbin/$MAIN.txt | |||
echo Converting ASCII output to bitstream | |||
icepack txtbin/$MAIN.txt txtbin/$MAIN.bin | |||
echo Sending bitstream to device | |||
iceprog ${ICEPROG_ARGS} $MAIN.bin | |||
@ -0,0 +1,25 @@ | |||
set_io CLK_IN 21 | |||
set_io J3_10 44 | |||
set_io J3_9 45 | |||
set_io J3_8 47 | |||
set_io J3_7 48 | |||
set_io J3_6 56 | |||
set_io J3_5 60 | |||
set_io J3_4 61 | |||
set_io J3_3 62 | |||
set_io GLED5 95 | |||
set_io RLED4 96 | |||
set_io RLED3 97 | |||
set_io RLED2 98 | |||
set_io RLED1 99 | |||
set_io IR_TX 105 | |||
set_io IR_RX 106 | |||
set_io IR_SD 107 | |||
set_io J1_3 112 | |||
set_io J1_4 113 | |||
set_io J1_5 114 | |||
set_io J1_6 115 | |||
set_io J1_7 116 | |||
set_io J1_8 117 | |||
set_io J1_9 118 | |||
set_io J1_10 119 |
@ -0,0 +1,236 @@ | |||
# Generated by Yosys 0.9+2406 (git sha1 eed05953, clang 3.8.1-24 -fPIC -Os) | |||
.model Blink | |||
.inputs CLK_IN | |||
.outputs GLED5 RLED1 RLED2 RLED3 RLED4 | |||
.names $false | |||
.names $true | |||
1 | |||
.names $undef | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[23] Q=RLED1 | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_LUT4 I0=$false I1=$false I2=RLED1 I3=RLED1_SB_LUT4_I2_I3[23] O=RLED1_SB_LUT4_I2_O[23] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=counter[0] O=RLED1_SB_LUT4_I2_O[0] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" | |||
.param LUT_INIT 0000000011111111 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[10] I3=RLED1_SB_LUT4_I2_I3[10] O=RLED1_SB_LUT4_I2_O[10] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[22] I3=RLED1_SB_LUT4_I2_I3[22] O=RLED1_SB_LUT4_I2_O[22] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[21] I3=RLED1_SB_LUT4_I2_I3[21] O=RLED1_SB_LUT4_I2_O[21] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[20] I3=RLED1_SB_LUT4_I2_I3[20] O=RLED1_SB_LUT4_I2_O[20] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[1] I3=counter[0] O=RLED1_SB_LUT4_I2_O[1] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[19] I3=RLED1_SB_LUT4_I2_I3[19] O=RLED1_SB_LUT4_I2_O[19] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[18] I3=RLED1_SB_LUT4_I2_I3[18] O=RLED1_SB_LUT4_I2_O[18] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[17] I3=RLED1_SB_LUT4_I2_I3[17] O=RLED1_SB_LUT4_I2_O[17] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[16] I3=RLED1_SB_LUT4_I2_I3[16] O=RLED1_SB_LUT4_I2_O[16] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[15] I3=RLED1_SB_LUT4_I2_I3[15] O=RLED1_SB_LUT4_I2_O[15] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[14] I3=RLED1_SB_LUT4_I2_I3[14] O=RLED1_SB_LUT4_I2_O[14] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[9] I3=RLED1_SB_LUT4_I2_I3[9] O=RLED1_SB_LUT4_I2_O[9] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[13] I3=RLED1_SB_LUT4_I2_I3[13] O=RLED1_SB_LUT4_I2_O[13] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[12] I3=RLED1_SB_LUT4_I2_I3[12] O=RLED1_SB_LUT4_I2_O[12] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[11] I3=RLED1_SB_LUT4_I2_I3[11] O=RLED1_SB_LUT4_I2_O[11] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[8] I3=RLED1_SB_LUT4_I2_I3[8] O=RLED1_SB_LUT4_I2_O[8] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[7] I3=RLED1_SB_LUT4_I2_I3[7] O=RLED1_SB_LUT4_I2_O[7] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[6] I3=RLED1_SB_LUT4_I2_I3[6] O=RLED1_SB_LUT4_I2_O[6] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[5] I3=RLED1_SB_LUT4_I2_I3[5] O=RLED1_SB_LUT4_I2_O[5] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[4] I3=RLED1_SB_LUT4_I2_I3[4] O=RLED1_SB_LUT4_I2_O[4] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[3] I3=RLED1_SB_LUT4_I2_I3[3] O=RLED1_SB_LUT4_I2_O[3] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=counter[2] I3=RLED1_SB_LUT4_I2_I3[2] O=RLED1_SB_LUT4_I2_O[2] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_CARRY CI=counter[0] CO=RLED1_SB_LUT4_I2_I3[2] I0=$false I1=counter[1] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[9] CO=RLED1_SB_LUT4_I2_I3[10] I0=$false I1=counter[9] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[8] CO=RLED1_SB_LUT4_I2_I3[9] I0=$false I1=counter[8] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[20] CO=RLED1_SB_LUT4_I2_I3[21] I0=$false I1=counter[20] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[19] CO=RLED1_SB_LUT4_I2_I3[20] I0=$false I1=counter[19] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[18] CO=RLED1_SB_LUT4_I2_I3[19] I0=$false I1=counter[18] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[17] CO=RLED1_SB_LUT4_I2_I3[18] I0=$false I1=counter[17] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[16] CO=RLED1_SB_LUT4_I2_I3[17] I0=$false I1=counter[16] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[15] CO=RLED1_SB_LUT4_I2_I3[16] I0=$false I1=counter[15] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[14] CO=RLED1_SB_LUT4_I2_I3[15] I0=$false I1=counter[14] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[13] CO=RLED1_SB_LUT4_I2_I3[14] I0=$false I1=counter[13] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[12] CO=RLED1_SB_LUT4_I2_I3[13] I0=$false I1=counter[12] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[11] CO=RLED1_SB_LUT4_I2_I3[12] I0=$false I1=counter[11] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[7] CO=RLED1_SB_LUT4_I2_I3[8] I0=$false I1=counter[7] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[10] CO=RLED1_SB_LUT4_I2_I3[11] I0=$false I1=counter[10] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[6] CO=RLED1_SB_LUT4_I2_I3[7] I0=$false I1=counter[6] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[5] CO=RLED1_SB_LUT4_I2_I3[6] I0=$false I1=counter[5] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[4] CO=RLED1_SB_LUT4_I2_I3[5] I0=$false I1=counter[4] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[3] CO=RLED1_SB_LUT4_I2_I3[4] I0=$false I1=counter[3] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[2] CO=RLED1_SB_LUT4_I2_I3[3] I0=$false I1=counter[2] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[22] CO=RLED1_SB_LUT4_I2_I3[23] I0=$false I1=counter[22] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=RLED1_SB_LUT4_I2_I3[21] CO=RLED1_SB_LUT4_I2_I3[22] I0=$false I1=counter[21] | |||
.attr src "blink.v:12.14-12.25|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[22] Q=counter[22] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[21] Q=counter[21] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[12] Q=counter[12] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[11] Q=counter[11] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[10] Q=counter[10] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[9] Q=counter[9] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[8] Q=counter[8] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[7] Q=counter[7] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[6] Q=counter[6] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[5] Q=counter[5] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[4] Q=counter[4] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[3] Q=counter[3] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[20] Q=counter[20] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[2] Q=counter[2] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[1] Q=counter[1] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[0] Q=counter[0] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[19] Q=counter[19] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[18] Q=counter[18] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[17] Q=counter[17] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[16] Q=counter[16] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[15] Q=counter[15] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[14] Q=counter[14] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=RLED1_SB_LUT4_I2_O[13] Q=counter[13] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "blink.v:11.2-12.26|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.names $false RLED1_SB_LUT4_I2_I3[0] | |||
1 1 | |||
.names counter[0] RLED1_SB_LUT4_I2_I3[1] | |||
1 1 | |||
.names $undef GLED5 | |||
1 1 | |||
.names $undef RLED2 | |||
1 1 | |||
.names $undef RLED3 | |||
1 1 | |||
.names $undef RLED4 | |||
1 1 | |||
.names RLED1 counter[23] | |||
1 1 | |||
.end |
@ -0,0 +1,18 @@ | |||
#!/bin/bash -x | |||
#adapted from https://github.com/leedowthwaite/HelloIce | |||
#changes: separate folder for dev files | |||
#simplified bash script | |||
#added vhdl2verilog per: https://github.com/4ilo/Ice40-vhdl-example | |||
mkdir txtbin | |||
echo convert vhdl to verilog | |||
./vhd2vl_bin $1.vhd $1.v | |||
echo Using yosys to synthesize design | |||
yosys -p "synth_ice40 -blif txtbin/$1.blif" ./$1.v | |||
echo Place and route with arachne-pnr | |||
arachne-pnr -d 1k -p icestick.pcf txtbin/$1.blif -o txtbin/$1.txt | |||
echo Converting ASCII output to bitstream | |||
icepack txtbin/$1.txt txtbin/$1.bin | |||
echo Sending bitstream to device | |||
iceprog ${ICEPROG_ARGS} txtbin/$1.bin | |||
@ -0,0 +1,41 @@ | |||
// File counter.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator | |||
// vhd2vl settings: | |||
// * Verilog Module Declaration Style: 2001 | |||
// vhd2vl is Free (libre) Software: | |||
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd | |||
// http://www.ocean-logic.com | |||
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc | |||
// Modifications (C) 2010 Shankar Giri | |||
// Modifications Copyright (C) 2002-2017 Larry Doolittle | |||
// http://doolittle.icarus.com/~larry/vhd2vl/ | |||
// Modifications (C) 2017 Rodrigo A. Melo | |||
// | |||
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting | |||
// Verilog for correctness, ideally with a formal verification tool. | |||
// | |||
// You are welcome to redistribute vhd2vl under certain conditions. | |||
// See the license (GPLv2) file included with the source for details. | |||
// The result of translation follows. Its copyright status should be | |||
// considered unchanged from the original VHDL. | |||
// no timescale needed | |||
module counter( | |||
input wire CLK_IN, | |||
output wire [3:0] RLED | |||
); | |||
reg [3:0] pres_count; wire [3:0] next_count; | |||
assign RLED = pres_count; | |||
always @(posedge CLK_IN) begin | |||
pres_count <= pres_count + 1; | |||
end | |||
endmodule |
@ -0,0 +1,27 @@ | |||
library ieee ; | |||
use ieee.std_logic_1164.all ; | |||
use ieee.numeric_std.all ; | |||
entity counter is | |||
port ( | |||
CLK_IN: in std_logic; | |||
RLED: out std_logic_vector(3 downto 0) | |||
); | |||
end counter ; | |||
architecture behav of counter is | |||
signal pres_count, next_count: std_logic_vector(3 downto 0); | |||
begin | |||
RLED <= pres_count; | |||
sync_count: process(CLK_IN) | |||
begin | |||
if(rising_edge(CLK_IN)) then | |||
pres_count <= pres_count + 1; | |||
end if; | |||
end process sync_count; | |||
end architecture; |
@ -0,0 +1,41 @@ | |||
// File counter_slow.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator | |||
// vhd2vl settings: | |||
// * Verilog Module Declaration Style: 2001 | |||
// vhd2vl is Free (libre) Software: | |||
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd | |||
// http://www.ocean-logic.com | |||
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc | |||
// Modifications (C) 2010 Shankar Giri | |||
// Modifications Copyright (C) 2002-2017 Larry Doolittle | |||
// http://doolittle.icarus.com/~larry/vhd2vl/ | |||
// Modifications (C) 2017 Rodrigo A. Melo | |||
// | |||
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting | |||
// Verilog for correctness, ideally with a formal verification tool. | |||
// | |||
// You are welcome to redistribute vhd2vl under certain conditions. | |||
// See the license (GPLv2) file included with the source for details. | |||
// The result of translation follows. Its copyright status should be | |||
// considered unchanged from the original VHDL. | |||
// no timescale needed | |||
module counter( | |||
input wire CLK_IN, | |||
output wire [3:0] RLED | |||
); | |||
reg [24:0] pres_count; wire [24:0] next_count; | |||
assign RLED = pres_count[20:17]; | |||
always @(posedge CLK_IN) begin | |||
pres_count <= pres_count + 1; | |||
end | |||
endmodule |
@ -0,0 +1,27 @@ | |||
library ieee ; | |||
use ieee.std_logic_1164.all ; | |||
use ieee.numeric_std.all ; | |||
entity counter is | |||
port ( | |||
CLK_IN: in std_logic; | |||
RLED: out std_logic_vector(3 downto 0) | |||
); | |||
end counter ; | |||
architecture behav of counter is | |||
signal pres_count, next_count: std_logic_vector(24 downto 0); | |||
begin | |||
RLED <= pres_count(20 downto 17); | |||
sync_count: process(CLK_IN) | |||
begin | |||
if(rising_edge(CLK_IN)) then | |||
pres_count <= pres_count + 1; | |||
end if; | |||
end process sync_count; | |||
end architecture; |
@ -0,0 +1,25 @@ | |||
set_io CLK_IN 21 | |||
set_io J3_10 44 | |||
set_io J3_9 45 | |||
set_io J3_8 47 | |||
set_io J3_7 48 | |||
set_io J3_6 56 | |||
set_io J3_5 60 | |||
set_io J3_4 61 | |||
set_io J3_3 62 | |||
set_io GLED5 95 | |||
set_io RLED[3] 96 | |||
set_io RLED[2] 97 | |||
set_io RLED[1] 98 | |||
set_io RLED[0] 99 | |||
set_io IR_TX 105 | |||
set_io IR_RX 106 | |||
set_io IR_SD 107 | |||
set_io J1_3 112 | |||
set_io J1_4 113 | |||
set_io J1_5 114 | |||
set_io J1_6 115 | |||
set_io J1_7 116 | |||
set_io J1_8 117 | |||
set_io J1_9 118 | |||
set_io J1_10 119 |
@ -0,0 +1,25 @@ | |||
set_io CLK_IN 21 | |||
set_io J3_10 44 | |||
set_io J3_9 45 | |||
set_io J3_8 47 | |||
set_io J3_7 48 | |||
set_io J3_6 56 | |||
set_io J3_5 60 | |||
set_io J3_4 61 | |||
set_io J3_3 62 | |||
set_io GLED5 95 | |||
set_io RLED[3] 96 | |||
set_io RLED[2] 97 | |||
set_io RLED[1] 98 | |||
set_io RLED[0] 99 | |||
set_io IR_TX 105 | |||
set_io IR_RX 106 | |||
set_io IR_SD 107 | |||
set_io J1_3 112 | |||
set_io J1_4 113 | |||
set_io J1_5 114 | |||
set_io J1_6 115 | |||
set_io J1_7 116 | |||
set_io J1_8 117 | |||
set_io J1_9 118 | |||
set_io J1_10 119 |
@ -0,0 +1,8 @@ | |||
set_io clk 21 | |||
set_io up 44 | |||
set_io rst 45 | |||
set_io count_out[0] 99 #PIO3_1A | |||
set_io count_out[1] 98 #PIO3_1B | |||
set_io count_out[2] 97 #PIO3_2A | |||
set_io count_out[3] 96 #PIO3_2B |
@ -0,0 +1,54 @@ | |||
# Generated by Yosys 0.9+2406 (git sha1 eed05953, clang 3.8.1-24 -fPIC -Os) | |||
.model counter | |||
.inputs CLK_IN | |||
.outputs RLED[0] RLED[1] RLED[2] RLED[3] | |||
.names $false | |||
.names $true | |||
1 | |||
.names $undef | |||
.gate SB_CARRY CI=pres_count[0] CO=pres_count_SB_CARRY_CI_CO[2] I0=$false I1=pres_count[1] | |||
.attr src "./counter.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[2] CO=pres_count_SB_CARRY_CI_CO[3] I0=$false I1=pres_count[2] | |||
.attr src "./counter.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[3] Q=pres_count[3] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[2] Q=pres_count[2] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[1] Q=pres_count[1] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[0] Q=pres_count[0] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[1] I3=pres_count[0] O=pres_count_SB_DFF_Q_D[1] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[3] I3=pres_count_SB_CARRY_CI_CO[3] O=pres_count_SB_DFF_Q_D[3] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[2] I3=pres_count_SB_CARRY_CI_CO[2] O=pres_count_SB_DFF_Q_D[2] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=pres_count[0] O=pres_count_SB_DFF_Q_D[0] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" | |||
.param LUT_INIT 0000000011111111 | |||
.names $false pres_count_SB_CARRY_CI_CO[0] | |||
1 1 | |||
.names pres_count[0] pres_count_SB_CARRY_CI_CO[1] | |||
1 1 | |||
.names pres_count[0] RLED[0] | |||
1 1 | |||
.names pres_count[1] RLED[1] | |||
1 1 | |||
.names pres_count[2] RLED[2] | |||
1 1 | |||
.names pres_count[3] RLED[3] | |||
1 1 | |||
.end |
@ -0,0 +1,207 @@ | |||
# Generated by Yosys 0.9+2406 (git sha1 eed05953, clang 3.8.1-24 -fPIC -Os) | |||
.model counter | |||
.inputs CLK_IN | |||
.outputs RLED[0] RLED[1] RLED[2] RLED[3] | |||
.names $false | |||
.names $true | |||
1 | |||
.names $undef | |||
.gate SB_CARRY CI=pres_count[0] CO=pres_count_SB_CARRY_CI_CO[2] I0=$false I1=pres_count[1] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[9] CO=pres_count_SB_CARRY_CI_CO[10] I0=$false I1=pres_count[9] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[8] CO=pres_count_SB_CARRY_CI_CO[9] I0=$false I1=pres_count[8] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[17] CO=pres_count_SB_CARRY_CI_CO[18] I0=$false I1=pres_count[17] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[16] CO=pres_count_SB_CARRY_CI_CO[17] I0=$false I1=pres_count[16] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[15] CO=pres_count_SB_CARRY_CI_CO[16] I0=$false I1=pres_count[15] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[14] CO=pres_count_SB_CARRY_CI_CO[15] I0=$false I1=pres_count[14] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[13] CO=pres_count_SB_CARRY_CI_CO[14] I0=$false I1=pres_count[13] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[12] CO=pres_count_SB_CARRY_CI_CO[13] I0=$false I1=pres_count[12] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[11] CO=pres_count_SB_CARRY_CI_CO[12] I0=$false I1=pres_count[11] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[10] CO=pres_count_SB_CARRY_CI_CO[11] I0=$false I1=pres_count[10] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[7] CO=pres_count_SB_CARRY_CI_CO[8] I0=$false I1=pres_count[7] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[6] CO=pres_count_SB_CARRY_CI_CO[7] I0=$false I1=pres_count[6] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[5] CO=pres_count_SB_CARRY_CI_CO[6] I0=$false I1=pres_count[5] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[4] CO=pres_count_SB_CARRY_CI_CO[5] I0=$false I1=pres_count[4] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[3] CO=pres_count_SB_CARRY_CI_CO[4] I0=$false I1=pres_count[3] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[2] CO=pres_count_SB_CARRY_CI_CO[3] I0=$false I1=pres_count[2] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[19] CO=pres_count_SB_CARRY_CI_CO[20] I0=$false I1=pres_count[19] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_CARRY CI=pres_count_SB_CARRY_CI_CO[18] CO=pres_count_SB_CARRY_CI_CO[19] I0=$false I1=pres_count[18] | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[20] Q=pres_count[20] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[19] Q=pres_count[19] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[10] Q=pres_count[10] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[9] Q=pres_count[9] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[8] Q=pres_count[8] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[7] Q=pres_count[7] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[6] Q=pres_count[6] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[5] Q=pres_count[5] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[4] Q=pres_count[4] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[3] Q=pres_count[3] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[2] Q=pres_count[2] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[1] Q=pres_count[1] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[18] Q=pres_count[18] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[0] Q=pres_count[0] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[17] Q=pres_count[17] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[16] Q=pres_count[16] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[15] Q=pres_count[15] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[14] Q=pres_count[14] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[13] Q=pres_count[13] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[12] Q=pres_count[12] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_DFF C=CLK_IN D=pres_count_SB_DFF_Q_D[11] Q=pres_count[11] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:36.3-38.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[10] I3=pres_count_SB_CARRY_CI_CO[10] O=pres_count_SB_DFF_Q_D[10] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[9] I3=pres_count_SB_CARRY_CI_CO[9] O=pres_count_SB_DFF_Q_D[9] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[1] I3=pres_count[0] O=pres_count_SB_DFF_Q_D[1] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[19] I3=pres_count_SB_CARRY_CI_CO[19] O=pres_count_SB_DFF_Q_D[19] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[18] I3=pres_count_SB_CARRY_CI_CO[18] O=pres_count_SB_DFF_Q_D[18] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[17] I3=pres_count_SB_CARRY_CI_CO[17] O=pres_count_SB_DFF_Q_D[17] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[16] I3=pres_count_SB_CARRY_CI_CO[16] O=pres_count_SB_DFF_Q_D[16] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[15] I3=pres_count_SB_CARRY_CI_CO[15] O=pres_count_SB_DFF_Q_D[15] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[14] I3=pres_count_SB_CARRY_CI_CO[14] O=pres_count_SB_DFF_Q_D[14] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[13] I3=pres_count_SB_CARRY_CI_CO[13] O=pres_count_SB_DFF_Q_D[13] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[12] I3=pres_count_SB_CARRY_CI_CO[12] O=pres_count_SB_DFF_Q_D[12] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[11] I3=pres_count_SB_CARRY_CI_CO[11] O=pres_count_SB_DFF_Q_D[11] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[8] I3=pres_count_SB_CARRY_CI_CO[8] O=pres_count_SB_DFF_Q_D[8] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[7] I3=pres_count_SB_CARRY_CI_CO[7] O=pres_count_SB_DFF_Q_D[7] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[6] I3=pres_count_SB_CARRY_CI_CO[6] O=pres_count_SB_DFF_Q_D[6] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[5] I3=pres_count_SB_CARRY_CI_CO[5] O=pres_count_SB_DFF_Q_D[5] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[4] I3=pres_count_SB_CARRY_CI_CO[4] O=pres_count_SB_DFF_Q_D[4] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[3] I3=pres_count_SB_CARRY_CI_CO[3] O=pres_count_SB_DFF_Q_D[3] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[2] I3=pres_count_SB_CARRY_CI_CO[2] O=pres_count_SB_DFF_Q_D[2] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=pres_count[20] I3=pres_count_SB_CARRY_CI_CO[20] O=pres_count_SB_DFF_Q_D[20] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "./counter_slow.v:37.19-37.33|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" | |||
.param LUT_INIT 0110100110010110 | |||
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=pres_count[0] O=pres_count_SB_DFF_Q_D[0] | |||
.attr module_not_derived 00000000000000000000000000000001 | |||
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" | |||
.param LUT_INIT 0000000011111111 | |||
.names $false pres_count_SB_CARRY_CI_CO[0] | |||
1 1 | |||
.names pres_count[0] pres_count_SB_CARRY_CI_CO[1] | |||
1 1 | |||
.names pres_count[17] RLED[0] | |||
1 1 | |||
.names pres_count[18] RLED[1] | |||
1 1 | |||
.names pres_count[19] RLED[2] | |||
1 1 | |||
.names pres_count[20] RLED[3] | |||
1 1 | |||
.end |
@ -0,0 +1 @@ | |||
Subproject commit 37e3143395ce4e7d2f2e301e12a538caf52b983c |