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Electronics_Projects_2020/60hz_Divider/docs/fitting-report.log

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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: counta Date: 7-14-2020, 1:00AM
Device Used: XC9572XL-5-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
70 /72 ( 97%) 186 /360 ( 52%) 166/216 ( 77%) 70 /72 ( 97%) 11 /34 ( 32%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 33/54 38/90 7/ 9
FB2 18/18* 46/54 54/90 0/ 9
FB3 18/18* 45/54 49/90 2/ 9
FB4 16/18 42/54 45/90 2/ 7
----- ----- ----- -----
70/72 166/216 186/360 11/34
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 8 28
Output : 9 9 | GCK/IO : 3 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 11 11
** Power Data **
There are 70 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'counta.ise'.
WARNING:Cpld:1007 - Removing unused input(s) 'SWITCH'. The input(s) are unused
after optimization. Please verify functionality via simulation.
************************* Summary of Mapped Logic ************************
** 9 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
LED<0> 2 19 FB1_6 41 I/O O STD FAST RESET
LED<1> 2 20 FB1_8 42 I/O O STD FAST RESET
LED<2> 2 21 FB1_9 43 GCK/I/O O STD FAST RESET
LED<3> 2 22 FB1_11 44 GCK/I/O O STD FAST RESET
LED<4> 2 23 FB1_14 1 GCK/I/O O STD FAST RESET
LED<5> 2 24 FB1_15 2 I/O O STD FAST RESET
LED<6> 2 25 FB1_17 3 I/O O STD FAST RESET
LED<7> 2 26 FB3_2 5 I/O O STD FAST RESET
TX 7 20 FB3_5 6 I/O O STD FAST RESET
** 61 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
clkcounta<9> 2 10 FB1_1 STD RESET
clkcounta<8> 2 9 FB1_2 STD RESET
clkcounta<7> 2 8 FB1_3 STD RESET
clkcounta<6> 2 7 FB1_4 STD RESET
clkcounta<5> 2 6 FB1_5 STD RESET
clkcounta<4> 2 5 FB1_7 STD RESET
clkcounta<3> 2 4 FB1_10 STD RESET
clkcounta<2> 2 3 FB1_12 STD RESET
clkcounta<1> 2 2 FB1_13 STD RESET
testhzctr<7> 3 9 FB1_16 STD RESET
testhzctr<6> 3 8 FB1_18 STD RESET
storecounta<25> 3 29 FB2_1 STD RESET
storecounta<24> 3 29 FB2_2 STD RESET
storecounta<23> 3 29 FB2_3 STD RESET
storecounta<22> 3 29 FB2_4 STD RESET
storecounta<21> 3 29 FB2_5 STD RESET
storecounta<20> 3 29 FB2_6 STD RESET
storecounta<1> 3 29 FB2_7 STD RESET
storecounta<19> 3 29 FB2_8 STD RESET
storecounta<18> 3 29 FB2_9 STD RESET
storecounta<17> 3 29 FB2_10 STD RESET
storecounta<16> 3 29 FB2_11 STD RESET
storecounta<15> 3 29 FB2_12 STD RESET
storecounta<14> 3 29 FB2_13 STD RESET
storecounta<13> 3 29 FB2_14 STD RESET
storecounta<12> 3 29 FB2_15 STD RESET
storecounta<11> 3 29 FB2_16 STD RESET
storecounta<10> 3 29 FB2_17 STD RESET
storecounta<0> 3 29 FB2_18 STD RESET
clkcounta<17> 2 18 FB3_1 STD RESET
clkcounta<16> 2 17 FB3_3 STD RESET
clkcounta<15> 2 16 FB3_4 STD RESET
clkcounta<14> 2 15 FB3_6 STD RESET
clkcounta<13> 2 14 FB3_7 STD RESET
clkcounta<12> 2 13 FB3_8 STD RESET
clkcounta<11> 2 12 FB3_9 STD RESET
clkcounta<10> 2 11 FB3_10 STD RESET
testhzctr<9> 3 11 FB3_11 STD RESET
testhzctr<8> 3 10 FB3_12 STD RESET
testhzctr<15> 3 17 FB3_13 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
testhzctr<14> 3 16 FB3_14 STD RESET
testhzctr<13> 3 15 FB3_15 STD RESET
testhzctr<12> 3 14 FB3_16 STD RESET
testhzctr<11> 3 13 FB3_17 STD RESET
testhzctr<10> 3 12 FB3_18 STD RESET
clkcounta<0> 1 1 FB4_3 STD RESET
testhzctr<0> 2 2 FB4_4 STD RESET
uartnow<0> 3 29 FB4_5 STD RESET
testhzctr<5> 3 7 FB4_6 STD RESET
testhzctr<4> 3 6 FB4_7 STD RESET
testhzctr<3> 3 5 FB4_8 STD RESET
testhzctr<2> 3 4 FB4_9 STD RESET
testhzctr<1> 3 3 FB4_10 STD RESET
storecounta<9> 3 29 FB4_11 STD RESET
storecounta<8> 3 29 FB4_12 STD RESET
storecounta<7> 3 29 FB4_13 STD RESET
storecounta<6> 3 29 FB4_14 STD RESET
storecounta<5> 3 29 FB4_15 STD RESET
storecounta<4> 3 29 FB4_16 STD RESET
storecounta<3> 3 29 FB4_17 STD RESET
storecounta<2> 3 29 FB4_18 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
XSTALIN FB4_5 20 I/O I
HZIN FB4_8 21 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 33/21
Number of signals used by logic mapping into function block: 33
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
clkcounta<9> 2 0 0 3 FB1_1 (b) (b)
clkcounta<8> 2 0 0 3 FB1_2 39 I/O (b)
clkcounta<7> 2 0 0 3 FB1_3 (b) (b)
clkcounta<6> 2 0 0 3 FB1_4 (b) (b)
clkcounta<5> 2 0 0 3 FB1_5 40 I/O (b)
LED<0> 2 0 0 3 FB1_6 41 I/O O
clkcounta<4> 2 0 0 3 FB1_7 (b) (b)
LED<1> 2 0 0 3 FB1_8 42 I/O O
LED<2> 2 0 0 3 FB1_9 43 GCK/I/O O
clkcounta<3> 2 0 0 3 FB1_10 (b) (b)
LED<3> 2 0 0 3 FB1_11 44 GCK/I/O O
clkcounta<2> 2 0 0 3 FB1_12 (b) (b)
clkcounta<1> 2 0 0 3 FB1_13 (b) (b)
LED<4> 2 0 0 3 FB1_14 1 GCK/I/O O
LED<5> 2 0 0 3 FB1_15 2 I/O O
testhzctr<7> 3 0 0 2 FB1_16 (b) (b)
LED<6> 2 0 0 3 FB1_17 3 I/O O
testhzctr<6> 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: HZIN 12: clkcounta<12> 23: clkcounta<6>
2: LED<0> 13: clkcounta<13> 24: clkcounta<7>
3: LED<1> 14: clkcounta<14> 25: clkcounta<8>
4: LED<2> 15: clkcounta<15> 26: clkcounta<9>
5: LED<3> 16: clkcounta<16> 27: testhzctr<0>
6: LED<4> 17: clkcounta<17> 28: testhzctr<1>
7: LED<5> 18: clkcounta<1> 29: testhzctr<2>
8: XSTALIN 19: clkcounta<2> 30: testhzctr<3>
9: clkcounta<0> 20: clkcounta<3> 31: testhzctr<4>
10: clkcounta<10> 21: clkcounta<4> 32: testhzctr<5>
11: clkcounta<11> 22: clkcounta<5> 33: testhzctr<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
clkcounta<9> .......XX........XXXXXXXX............... 10
clkcounta<8> .......XX........XXXXXXX................ 9
clkcounta<7> .......XX........XXXXXX................. 8
clkcounta<6> .......XX........XXXXX.................. 7
clkcounta<5> .......XX........XXXX................... 6
LED<0> .......XXXXXXXXXXXXXXXXXXX.............. 19
clkcounta<4> .......XX........XXX.................... 5
LED<1> .X.....XXXXXXXXXXXXXXXXXXX.............. 20
LED<2> .XX....XXXXXXXXXXXXXXXXXXX.............. 21
clkcounta<3> .......XX........XX..................... 4
LED<3> .XXX...XXXXXXXXXXXXXXXXXXX.............. 22
clkcounta<2> .......XX........X...................... 3
clkcounta<1> .......XX............................... 2
LED<4> .XXXX..XXXXXXXXXXXXXXXXXXX.............. 23
LED<5> .XXXXX.XXXXXXXXXXXXXXXXXXX.............. 24
testhzctr<7> X......X..................XXXXXXX....... 9
LED<6> .XXXXXXXXXXXXXXXXXXXXXXXXX.............. 25
testhzctr<6> X......X..................XXXXXX........ 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 46/8
Number of signals used by logic mapping into function block: 46
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
storecounta<25> 3 0 0 2 FB2_1 (b) (b)
storecounta<24> 3 0 0 2 FB2_2 29 I/O (b)
storecounta<23> 3 0 0 2 FB2_3 (b) (b)
storecounta<22> 3 0 0 2 FB2_4 (b) (b)
storecounta<21> 3 0 0 2 FB2_5 30 I/O (b)
storecounta<20> 3 0 0 2 FB2_6 31 I/O (b)
storecounta<1> 3 0 0 2 FB2_7 (b) (b)
storecounta<19> 3 0 0 2 FB2_8 32 I/O (b)
storecounta<18> 3 0 0 2 FB2_9 33 GSR/I/O (b)
storecounta<17> 3 0 0 2 FB2_10 (b) (b)
storecounta<16> 3 0 0 2 FB2_11 34 GTS/I/O (b)
storecounta<15> 3 0 0 2 FB2_12 (b) (b)
storecounta<14> 3 0 0 2 FB2_13 (b) (b)
storecounta<13> 3 0 0 2 FB2_14 36 GTS/I/O (b)
storecounta<12> 3 0 0 2 FB2_15 37 I/O (b)
storecounta<11> 3 0 0 2 FB2_16 (b) (b)
storecounta<10> 3 0 0 2 FB2_17 38 I/O (b)
storecounta<0> 3 0 0 2 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: HZIN 17: clkcounta<15> 32: storecounta<1>
2: LED<0> 18: clkcounta<16> 33: storecounta<20>
3: LED<1> 19: clkcounta<17> 34: storecounta<21>
4: LED<2> 20: clkcounta<1> 35: storecounta<22>
5: LED<3> 21: storecounta<0> 36: storecounta<23>
6: LED<4> 22: storecounta<10> 37: storecounta<24>
7: LED<5> 23: storecounta<11> 38: storecounta<25>
8: LED<6> 24: storecounta<12> 39: storecounta<2>
9: LED<7> 25: storecounta<13> 40: storecounta<3>
10: XSTALIN 26: storecounta<14> 41: storecounta<4>
11: clkcounta<0> 27: storecounta<15> 42: storecounta<5>
12: clkcounta<10> 28: storecounta<16> 43: storecounta<6>
13: clkcounta<11> 29: storecounta<17> 44: storecounta<7>
14: clkcounta<12> 30: storecounta<18> 45: storecounta<8>
15: clkcounta<13> 31: storecounta<19> 46: storecounta<9>
16: clkcounta<14>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
storecounta<25> X.......XX..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<24> X......X.X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<23> X.....X..X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<22> X....X...X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<21> X...X....X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<20> X..X.....X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<1> X........X.........XXXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<19> X.X......X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<18> XX.......X..........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<17> X........X........X.XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<16> X........X.......X..XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<15> X........X......X...XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<14> X........X.....X....XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<13> X........X....X.....XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<12> X........X...X......XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<11> X........X..X.......XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<10> X........X.X........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
storecounta<0> X........XX.........XXXXXXXXXXXXXXXXXXXXXXXXXX.... 29
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 45/9
Number of signals used by logic mapping into function block: 45
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
clkcounta<17> 2 0 0 3 FB3_1 (b) (b)
LED<7> 2 0 0 3 FB3_2 5 I/O O
clkcounta<16> 2 0 0 3 FB3_3 (b) (b)
clkcounta<15> 2 0 \/1 2 FB3_4 (b) (b)
TX 7 2<- 0 0 FB3_5 6 I/O O
clkcounta<14> 2 0 /\1 2 FB3_6 (b) (b)
clkcounta<13> 2 0 0 3 FB3_7 (b) (b)
clkcounta<12> 2 0 0 3 FB3_8 7 I/O (b)
clkcounta<11> 2 0 0 3 FB3_9 8 I/O (b)
clkcounta<10> 2 0 0 3 FB3_10 (b) (b)
testhzctr<9> 3 0 0 2 FB3_11 12 I/O (b)
testhzctr<8> 3 0 0 2 FB3_12 (b) (b)
testhzctr<15> 3 0 0 2 FB3_13 (b) (b)
testhzctr<14> 3 0 0 2 FB3_14 13 I/O (b)
testhzctr<13> 3 0 0 2 FB3_15 14 I/O (b)
testhzctr<12> 3 0 0 2 FB3_16 18 I/O (b)
testhzctr<11> 3 0 0 2 FB3_17 16 I/O (b)
testhzctr<10> 3 0 0 2 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: HZIN 16: clkcounta<14> 31: testhzctr<11>
2: LED<0> 17: clkcounta<15> 32: testhzctr<12>
3: LED<1> 18: clkcounta<16> 33: testhzctr<13>
4: LED<2> 19: clkcounta<17> 34: testhzctr<14>
5: LED<3> 20: clkcounta<1> 35: testhzctr<15>
6: LED<4> 21: clkcounta<2> 36: testhzctr<1>
7: LED<5> 22: clkcounta<3> 37: testhzctr<2>
8: LED<6> 23: clkcounta<4> 38: testhzctr<3>
9: TX 24: clkcounta<5> 39: testhzctr<4>
10: XSTALIN 25: clkcounta<6> 40: testhzctr<5>
11: clkcounta<0> 26: clkcounta<7> 41: testhzctr<6>
12: clkcounta<10> 27: clkcounta<8> 42: testhzctr<7>
13: clkcounta<11> 28: clkcounta<9> 43: testhzctr<8>
14: clkcounta<12> 29: testhzctr<0> 44: testhzctr<9>
15: clkcounta<13> 30: testhzctr<10> 45: uartnow<0>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
clkcounta<17> .........XXXXXXXXX.XXXXXXXXX...................... 18
LED<7> .XXXXXXX.XXXXXXXXXXXXXXXXXXX...................... 26
clkcounta<16> .........XXXXXXXX..XXXXXXXXX...................... 17
clkcounta<15> .........XXXXXXX...XXXXXXXXX...................... 16
TX X.......XX..................XXXXXXXXXXXXXXXXX..... 20
clkcounta<14> .........XXXXXX....XXXXXXXXX...................... 15
clkcounta<13> .........XXXXX.....XXXXXXXXX...................... 14
clkcounta<12> .........XXXX......XXXXXXXXX...................... 13
clkcounta<11> .........XXX.......XXXXXXXXX...................... 12
clkcounta<10> .........XX........XXXXXXXXX...................... 11
testhzctr<9> X........X..................X......XXXXXXXX....... 11
testhzctr<8> X........X..................X......XXXXXXX........ 10
testhzctr<15> X........X..................XXXXXX.XXXXXXXXX...... 17
testhzctr<14> X........X..................XXXXX..XXXXXXXXX...... 16
testhzctr<13> X........X..................XXXX...XXXXXXXXX...... 15
testhzctr<12> X........X..................XXX....XXXXXXXXX...... 14
testhzctr<11> X........X..................XX.....XXXXXXXXX...... 13
testhzctr<10> X........X..................X......XXXXXXXXX...... 12
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 42/12
Number of signals used by logic mapping into function block: 42
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 19 I/O
clkcounta<0> 1 0 0 4 FB4_3 (b) (b)
testhzctr<0> 2 0 0 3 FB4_4 (b) (b)
uartnow<0> 3 0 0 2 FB4_5 20 I/O I
testhzctr<5> 3 0 0 2 FB4_6 (b) (b)
testhzctr<4> 3 0 0 2 FB4_7 (b) (b)
testhzctr<3> 3 0 0 2 FB4_8 21 I/O I
testhzctr<2> 3 0 0 2 FB4_9 (b) (b)
testhzctr<1> 3 0 0 2 FB4_10 (b) (b)
storecounta<9> 3 0 0 2 FB4_11 22 I/O (b)
storecounta<8> 3 0 0 2 FB4_12 (b) (b)
storecounta<7> 3 0 0 2 FB4_13 (b) (b)
storecounta<6> 3 0 0 2 FB4_14 23 I/O (b)
storecounta<5> 3 0 0 2 FB4_15 27 I/O (b)
storecounta<4> 3 0 0 2 FB4_16 (b) (b)
storecounta<3> 3 0 0 2 FB4_17 28 I/O (b)
storecounta<2> 3 0 0 2 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: HZIN 15: storecounta<13> 29: storecounta<2>
2: XSTALIN 16: storecounta<14> 30: storecounta<3>
3: clkcounta<2> 17: storecounta<15> 31: storecounta<4>
4: clkcounta<3> 18: storecounta<16> 32: storecounta<5>
5: clkcounta<4> 19: storecounta<17> 33: storecounta<6>
6: clkcounta<5> 20: storecounta<18> 34: storecounta<7>
7: clkcounta<6> 21: storecounta<19> 35: storecounta<8>
8: clkcounta<7> 22: storecounta<1> 36: storecounta<9>
9: clkcounta<8> 23: storecounta<20> 37: testhzctr<0>
10: clkcounta<9> 24: storecounta<21> 38: testhzctr<1>
11: storecounta<0> 25: storecounta<22> 39: testhzctr<2>
12: storecounta<10> 26: storecounta<23> 40: testhzctr<3>
13: storecounta<11> 27: storecounta<24> 41: testhzctr<4>
14: storecounta<12> 28: storecounta<25> 42: uartnow<0>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
clkcounta<0> .X................................................ 1
testhzctr<0> XX................................................ 2
uartnow<0> XX........XXXXXXXXXXXXXXXXXXXXXXXXXX.....X........ 29
testhzctr<5> XX..................................XXXXX......... 7
testhzctr<4> XX..................................XXXX.......... 6
testhzctr<3> XX..................................XXX........... 5
testhzctr<2> XX..................................XX............ 4
testhzctr<1> XX..................................X............. 3
storecounta<9> XX.......XXXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<8> XX......X.XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<7> XX.....X..XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<6> XX....X...XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<5> XX...X....XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<4> XX..X.....XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<3> XX.X......XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
storecounta<2> XXX.......XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 29
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_LED0: FTCPE port map (LED(0),LED_T(0),XSTALIN,'0','0');
LED_T(0) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND clkcounta(15) AND
clkcounta(16) AND clkcounta(17) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),XSTALIN,'0','0');
LED_T(1) <= (LED(0) AND clkcounta(0) AND clkcounta(10) AND
clkcounta(11) AND clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND
clkcounta(15) AND clkcounta(16) AND clkcounta(17) AND clkcounta(1) AND
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_LED2: FTCPE port map (LED(2),LED_T(2),XSTALIN,'0','0');
LED_T(2) <= (LED(0) AND LED(1) AND clkcounta(0) AND clkcounta(10) AND
clkcounta(11) AND clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND
clkcounta(15) AND clkcounta(16) AND clkcounta(17) AND clkcounta(1) AND
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_LED3: FTCPE port map (LED(3),LED_T(3),XSTALIN,'0','0');
LED_T(3) <= (LED(0) AND LED(1) AND LED(2) AND clkcounta(0) AND
clkcounta(10) AND clkcounta(11) AND clkcounta(12) AND clkcounta(13) AND
clkcounta(14) AND clkcounta(15) AND clkcounta(16) AND clkcounta(17) AND
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
clkcounta(9));
FTCPE_LED4: FTCPE port map (LED(4),LED_T(4),XSTALIN,'0','0');
LED_T(4) <= (LED(0) AND LED(1) AND LED(2) AND LED(3) AND
clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND clkcounta(12) AND
clkcounta(13) AND clkcounta(14) AND clkcounta(15) AND clkcounta(16) AND
clkcounta(17) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
clkcounta(8) AND clkcounta(9));
FTCPE_LED5: FTCPE port map (LED(5),LED_T(5),XSTALIN,'0','0');
LED_T(5) <= (LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND
clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND clkcounta(12) AND
clkcounta(13) AND clkcounta(14) AND clkcounta(15) AND clkcounta(16) AND
clkcounta(17) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
clkcounta(8) AND clkcounta(9));
FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),XSTALIN,'0','0');
LED_T(6) <= (LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND
LED(5) AND clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND clkcounta(15) AND
clkcounta(16) AND clkcounta(17) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),XSTALIN,'0','0');
LED_T(7) <= (LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND
LED(5) AND LED(6) AND clkcounta(0) AND clkcounta(10) AND
clkcounta(11) AND clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND
clkcounta(15) AND clkcounta(16) AND clkcounta(17) AND clkcounta(1) AND
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FDCPE_TX: FDCPE port map (TX,TX_D,XSTALIN,'0','0');
TX_D <= ((NOT HZIN)
OR (NOT testhzctr(0) AND NOT testhzctr(10) AND NOT testhzctr(11) AND
NOT testhzctr(12) AND NOT testhzctr(13) AND NOT testhzctr(14) AND NOT testhzctr(2) AND
NOT testhzctr(3) AND NOT testhzctr(6) AND NOT testhzctr(7) AND NOT testhzctr(8) AND
NOT testhzctr(9) AND NOT testhzctr(15) AND NOT TX)
OR (NOT testhzctr(10) AND NOT testhzctr(11) AND NOT testhzctr(12) AND
NOT testhzctr(13) AND NOT testhzctr(14) AND NOT testhzctr(1) AND NOT testhzctr(2) AND
NOT testhzctr(3) AND NOT testhzctr(6) AND NOT testhzctr(7) AND NOT testhzctr(8) AND
NOT testhzctr(9) AND NOT testhzctr(15) AND NOT TX)
OR (NOT uartnow(0) AND NOT TX)
OR (NOT testhzctr(10) AND NOT testhzctr(11) AND NOT testhzctr(12) AND
NOT testhzctr(13) AND NOT testhzctr(14) AND NOT testhzctr(4) AND NOT testhzctr(6) AND
NOT testhzctr(7) AND NOT testhzctr(8) AND NOT testhzctr(9) AND NOT testhzctr(15) AND
NOT TX)
OR (NOT testhzctr(10) AND NOT testhzctr(11) AND NOT testhzctr(12) AND
NOT testhzctr(13) AND NOT testhzctr(14) AND NOT testhzctr(5) AND NOT testhzctr(6) AND
NOT testhzctr(7) AND NOT testhzctr(8) AND NOT testhzctr(9) AND NOT testhzctr(15) AND
NOT TX));
FTCPE_clkcounta0: FTCPE port map (clkcounta(0),'1',XSTALIN,'0','0');
FTCPE_clkcounta1: FTCPE port map (clkcounta(1),clkcounta(0),XSTALIN,'0','0');
FTCPE_clkcounta2: FTCPE port map (clkcounta(2),clkcounta_T(2),XSTALIN,'0','0');
clkcounta_T(2) <= (clkcounta(0) AND clkcounta(1));
FTCPE_clkcounta3: FTCPE port map (clkcounta(3),clkcounta_T(3),XSTALIN,'0','0');
clkcounta_T(3) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2));
FTCPE_clkcounta4: FTCPE port map (clkcounta(4),clkcounta_T(4),XSTALIN,'0','0');
clkcounta_T(4) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3));
FTCPE_clkcounta5: FTCPE port map (clkcounta(5),clkcounta_T(5),XSTALIN,'0','0');
clkcounta_T(5) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4));
FTCPE_clkcounta6: FTCPE port map (clkcounta(6),clkcounta_T(6),XSTALIN,'0','0');
clkcounta_T(6) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5));
FTCPE_clkcounta7: FTCPE port map (clkcounta(7),clkcounta_T(7),XSTALIN,'0','0');
clkcounta_T(7) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6));
FTCPE_clkcounta8: FTCPE port map (clkcounta(8),clkcounta_T(8),XSTALIN,'0','0');
clkcounta_T(8) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
clkcounta(7));
FTCPE_clkcounta9: FTCPE port map (clkcounta(9),clkcounta_T(9),XSTALIN,'0','0');
clkcounta_T(9) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
clkcounta(7) AND clkcounta(8));
FTCPE_clkcounta10: FTCPE port map (clkcounta(10),clkcounta_T(10),XSTALIN,'0','0');
clkcounta_T(10) <= (clkcounta(0) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_clkcounta11: FTCPE port map (clkcounta(11),clkcounta_T(11),XSTALIN,'0','0');
clkcounta_T(11) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(1) AND
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_clkcounta12: FTCPE port map (clkcounta(12),clkcounta_T(12),XSTALIN,'0','0');
clkcounta_T(12) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
clkcounta(9));
FTCPE_clkcounta13: FTCPE port map (clkcounta(13),clkcounta_T(13),XSTALIN,'0','0');
clkcounta_T(13) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
clkcounta(8) AND clkcounta(9));
FTCPE_clkcounta14: FTCPE port map (clkcounta(14),clkcounta_T(14),XSTALIN,'0','0');
clkcounta_T(14) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(13) AND clkcounta(1) AND clkcounta(2) AND
clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND
clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_clkcounta15: FTCPE port map (clkcounta(15),clkcounta_T(15),XSTALIN,'0','0');
clkcounta_T(15) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND clkcounta(1) AND
clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND clkcounta(5) AND
clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND clkcounta(9));
FTCPE_clkcounta16: FTCPE port map (clkcounta(16),clkcounta_T(16),XSTALIN,'0','0');
clkcounta_T(16) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND clkcounta(15) AND
clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND clkcounta(4) AND
clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND clkcounta(8) AND
clkcounta(9));
FTCPE_clkcounta17: FTCPE port map (clkcounta(17),clkcounta_T(17),XSTALIN,'0','0');
clkcounta_T(17) <= (clkcounta(0) AND clkcounta(10) AND clkcounta(11) AND
clkcounta(12) AND clkcounta(13) AND clkcounta(14) AND clkcounta(15) AND
clkcounta(16) AND clkcounta(1) AND clkcounta(2) AND clkcounta(3) AND
clkcounta(4) AND clkcounta(5) AND clkcounta(6) AND clkcounta(7) AND
clkcounta(8) AND clkcounta(9));
FDCPE_storecounta0: FDCPE port map (storecounta(0),storecounta_D(0),XSTALIN,'0','0');
storecounta_D(0) <= ((HZIN AND storecounta(0))
OR (HZIN AND NOT storecounta(10) AND NOT storecounta(11) AND
NOT storecounta(12) AND NOT storecounta(13) AND NOT storecounta(14) AND
NOT storecounta(15) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(0)));
FDCPE_storecounta1: FDCPE port map (storecounta(1),storecounta_D(1),XSTALIN,'0','0');
storecounta_D(1) <= ((HZIN AND storecounta(1))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(1)));
FDCPE_storecounta2: FDCPE port map (storecounta(2),storecounta_D(2),XSTALIN,'0','0');
storecounta_D(2) <= ((HZIN AND storecounta(2))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(2)));
FDCPE_storecounta3: FDCPE port map (storecounta(3),storecounta_D(3),XSTALIN,'0','0');
storecounta_D(3) <= ((HZIN AND storecounta(3))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(3)));
FDCPE_storecounta4: FDCPE port map (storecounta(4),storecounta_D(4),XSTALIN,'0','0');
storecounta_D(4) <= ((HZIN AND storecounta(4))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(4)));
FDCPE_storecounta5: FDCPE port map (storecounta(5),storecounta_D(5),XSTALIN,'0','0');
storecounta_D(5) <= ((HZIN AND storecounta(5))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(5)));
FDCPE_storecounta6: FDCPE port map (storecounta(6),storecounta_D(6),XSTALIN,'0','0');
storecounta_D(6) <= ((HZIN AND storecounta(6))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND
NOT storecounta(5) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(6)));
FDCPE_storecounta7: FDCPE port map (storecounta(7),storecounta_D(7),XSTALIN,'0','0');
storecounta_D(7) <= ((HZIN AND storecounta(7))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND
NOT storecounta(5) AND NOT storecounta(6) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(7)));
FDCPE_storecounta8: FDCPE port map (storecounta(8),storecounta_D(8),XSTALIN,'0','0');
storecounta_D(8) <= ((HZIN AND storecounta(8))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND
NOT storecounta(5) AND NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(9) AND
clkcounta(8)));
FDCPE_storecounta9: FDCPE port map (storecounta(9),storecounta_D(9),XSTALIN,'0','0');
storecounta_D(9) <= ((HZIN AND storecounta(9))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND
NOT storecounta(5) AND NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND
clkcounta(9)));
FDCPE_storecounta10: FDCPE port map (storecounta(10),storecounta_D(10),XSTALIN,'0','0');
storecounta_D(10) <= ((HZIN AND storecounta(10))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(11) AND
NOT storecounta(12) AND NOT storecounta(13) AND NOT storecounta(14) AND
NOT storecounta(15) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(10)));
FDCPE_storecounta11: FDCPE port map (storecounta(11),storecounta_D(11),XSTALIN,'0','0');
storecounta_D(11) <= ((HZIN AND storecounta(11))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(12) AND NOT storecounta(13) AND NOT storecounta(14) AND
NOT storecounta(15) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(11)));
FDCPE_storecounta12: FDCPE port map (storecounta(12),storecounta_D(12),XSTALIN,'0','0');
storecounta_D(12) <= ((HZIN AND storecounta(12))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(13) AND NOT storecounta(14) AND
NOT storecounta(15) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(12)));
FDCPE_storecounta13: FDCPE port map (storecounta(13),storecounta_D(13),XSTALIN,'0','0');
storecounta_D(13) <= ((HZIN AND storecounta(13))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(14) AND
NOT storecounta(15) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(13)));
FDCPE_storecounta14: FDCPE port map (storecounta(14),storecounta_D(14),XSTALIN,'0','0');
storecounta_D(14) <= ((HZIN AND storecounta(14))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(15) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(14)));
FDCPE_storecounta15: FDCPE port map (storecounta(15),storecounta_D(15),XSTALIN,'0','0');
storecounta_D(15) <= ((HZIN AND storecounta(15))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(16) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(15)));
FDCPE_storecounta16: FDCPE port map (storecounta(16),storecounta_D(16),XSTALIN,'0','0');
storecounta_D(16) <= ((HZIN AND storecounta(16))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(17) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(16)));
FDCPE_storecounta17: FDCPE port map (storecounta(17),storecounta_D(17),XSTALIN,'0','0');
storecounta_D(17) <= ((HZIN AND storecounta(17))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(18) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
clkcounta(17)));
FDCPE_storecounta18: FDCPE port map (storecounta(18),storecounta_D(18),XSTALIN,'0','0');
storecounta_D(18) <= ((HZIN AND storecounta(18))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(19) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(0)));
FDCPE_storecounta19: FDCPE port map (storecounta(19),storecounta_D(19),XSTALIN,'0','0');
storecounta_D(19) <= ((HZIN AND storecounta(19))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(1) AND
NOT storecounta(20) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(1)));
FDCPE_storecounta20: FDCPE port map (storecounta(20),storecounta_D(20),XSTALIN,'0','0');
storecounta_D(20) <= ((HZIN AND storecounta(20))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(21) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(2)));
FDCPE_storecounta21: FDCPE port map (storecounta(21),storecounta_D(21),XSTALIN,'0','0');
storecounta_D(21) <= ((HZIN AND storecounta(21))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(22) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(3)));
FDCPE_storecounta22: FDCPE port map (storecounta(22),storecounta_D(22),XSTALIN,'0','0');
storecounta_D(22) <= ((HZIN AND storecounta(22))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(23) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(4)));
FDCPE_storecounta23: FDCPE port map (storecounta(23),storecounta_D(23),XSTALIN,'0','0');
storecounta_D(23) <= ((HZIN AND storecounta(23))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(24) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(5)));
FDCPE_storecounta24: FDCPE port map (storecounta(24),storecounta_D(24),XSTALIN,'0','0');
storecounta_D(24) <= ((HZIN AND storecounta(24))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(25) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(6)));
FDCPE_storecounta25: FDCPE port map (storecounta(25),storecounta_D(25),XSTALIN,'0','0');
storecounta_D(25) <= ((HZIN AND storecounta(25))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND NOT storecounta(5) AND
NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND NOT storecounta(9) AND
LED(7)));
FTCPE_testhzctr0: FTCPE port map (testhzctr(0),'1',XSTALIN,'0','0',HZIN);
FTCPE_testhzctr1: FTCPE port map (testhzctr(1),testhzctr(0),XSTALIN,'0','0',HZIN);
FTCPE_testhzctr2: FTCPE port map (testhzctr(2),testhzctr_T(2),XSTALIN,'0','0',HZIN);
testhzctr_T(2) <= (testhzctr(0) AND testhzctr(1));
FTCPE_testhzctr3: FTCPE port map (testhzctr(3),testhzctr_T(3),XSTALIN,'0','0',HZIN);
testhzctr_T(3) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2));
FTCPE_testhzctr4: FTCPE port map (testhzctr(4),testhzctr_T(4),XSTALIN,'0','0',HZIN);
testhzctr_T(4) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3));
FTCPE_testhzctr5: FTCPE port map (testhzctr(5),testhzctr_T(5),XSTALIN,'0','0',HZIN);
testhzctr_T(5) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4));
FTCPE_testhzctr6: FTCPE port map (testhzctr(6),testhzctr_T(6),XSTALIN,'0','0',HZIN);
testhzctr_T(6) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4) AND testhzctr(5));
FTCPE_testhzctr7: FTCPE port map (testhzctr(7),testhzctr_T(7),XSTALIN,'0','0',HZIN);
testhzctr_T(7) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND testhzctr(6));
FTCPE_testhzctr8: FTCPE port map (testhzctr(8),testhzctr_T(8),XSTALIN,'0','0',HZIN);
testhzctr_T(8) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND testhzctr(6) AND
testhzctr(7));
FTCPE_testhzctr9: FTCPE port map (testhzctr(9),testhzctr_T(9),XSTALIN,'0','0',HZIN);
testhzctr_T(9) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND testhzctr(6) AND
testhzctr(7) AND testhzctr(8));
FTCPE_testhzctr10: FTCPE port map (testhzctr(10),testhzctr_T(10),XSTALIN,'0','0',HZIN);
testhzctr_T(10) <= (testhzctr(0) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND testhzctr(6) AND
testhzctr(7) AND testhzctr(8) AND testhzctr(9));
FTCPE_testhzctr11: FTCPE port map (testhzctr(11),testhzctr_T(11),XSTALIN,'0','0',HZIN);
testhzctr_T(11) <= (testhzctr(0) AND testhzctr(10) AND testhzctr(1) AND
testhzctr(2) AND testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND
testhzctr(6) AND testhzctr(7) AND testhzctr(8) AND testhzctr(9));
FTCPE_testhzctr12: FTCPE port map (testhzctr(12),testhzctr_T(12),XSTALIN,'0','0',HZIN);
testhzctr_T(12) <= (testhzctr(0) AND testhzctr(10) AND testhzctr(11) AND
testhzctr(1) AND testhzctr(2) AND testhzctr(3) AND testhzctr(4) AND
testhzctr(5) AND testhzctr(6) AND testhzctr(7) AND testhzctr(8) AND
testhzctr(9));
FTCPE_testhzctr13: FTCPE port map (testhzctr(13),testhzctr_T(13),XSTALIN,'0','0',HZIN);
testhzctr_T(13) <= (testhzctr(0) AND testhzctr(10) AND testhzctr(11) AND
testhzctr(12) AND testhzctr(1) AND testhzctr(2) AND testhzctr(3) AND
testhzctr(4) AND testhzctr(5) AND testhzctr(6) AND testhzctr(7) AND
testhzctr(8) AND testhzctr(9));
FTCPE_testhzctr14: FTCPE port map (testhzctr(14),testhzctr_T(14),XSTALIN,'0','0',HZIN);
testhzctr_T(14) <= (testhzctr(0) AND testhzctr(10) AND testhzctr(11) AND
testhzctr(12) AND testhzctr(13) AND testhzctr(1) AND testhzctr(2) AND
testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND testhzctr(6) AND
testhzctr(7) AND testhzctr(8) AND testhzctr(9));
FTCPE_testhzctr15: FTCPE port map (testhzctr(15),testhzctr_T(15),XSTALIN,'0','0',HZIN);
testhzctr_T(15) <= (testhzctr(0) AND testhzctr(10) AND testhzctr(11) AND
testhzctr(12) AND testhzctr(13) AND testhzctr(14) AND testhzctr(1) AND
testhzctr(2) AND testhzctr(3) AND testhzctr(4) AND testhzctr(5) AND
testhzctr(6) AND testhzctr(7) AND testhzctr(8) AND testhzctr(9));
FDCPE_uartnow0: FDCPE port map (uartnow(0),uartnow_D(0),XSTALIN,'0','0');
uartnow_D(0) <= ((HZIN AND uartnow(0))
OR (HZIN AND NOT storecounta(0) AND NOT storecounta(10) AND
NOT storecounta(11) AND NOT storecounta(12) AND NOT storecounta(13) AND
NOT storecounta(14) AND NOT storecounta(15) AND NOT storecounta(16) AND
NOT storecounta(17) AND NOT storecounta(18) AND NOT storecounta(19) AND
NOT storecounta(1) AND NOT storecounta(20) AND NOT storecounta(21) AND
NOT storecounta(22) AND NOT storecounta(23) AND NOT storecounta(24) AND
NOT storecounta(25) AND NOT storecounta(2) AND NOT storecounta(3) AND NOT storecounta(4) AND
NOT storecounta(5) AND NOT storecounta(6) AND NOT storecounta(7) AND NOT storecounta(8) AND
NOT storecounta(9)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572XL-5-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9572XL-5-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 LED<4> 23 KPR
2 LED<5> 24 TDO
3 LED<6> 25 GND
4 GND 26 VCC
5 LED<7> 27 KPR
6 TX 28 KPR
7 KPR 29 KPR
8 KPR 30 KPR
9 TDI 31 KPR
10 TMS 32 KPR
11 TCK 33 KPR
12 KPR 34 KPR
13 KPR 35 VCC
14 KPR 36 KPR
15 VCC 37 KPR
16 KPR 38 KPR
17 GND 39 KPR
18 KPR 40 KPR
19 KPR 41 LED<0>
20 XSTALIN 42 LED<1>
21 HZIN 43 LED<2>
22 KPR 44 LED<3>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-5-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25