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@ -67,8 +67,25 @@ Some of the lines have to be edited to allow for all digits to be read, and
also to lower intensity of display. I think also a component package (dark
grey clear plastic bag) in front of the leds with intensity 1 is about right.
\subsection{CPLDs}
\begin{verbatim}
http://dangerousprototypes.com/docs/Xilinx_CPLDs:_XC9500_vs_CoolRunner-II
https://www.eevblog.com/forum/fpga/what-are-cplds-do-they-still-play-a-role-how-to-program-them/msg3084581/#msg3084581
https://www.seeedstudio.com/XC9572XL-CPLD-development-board-v1b-p-799.html
\end{verbatim}
dangerous prototypes has a few
including the xc2, the xc95, and the coolrunner.
i wanted xc95, so they have one for \$12. not bad.
looks like bus pirate can program... But I ended up using a Xilinx USB Platform Cable.
\subsection{CPLD Programming}
Using the XC9500XL series. This chip has some limitations - which are good.
As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.

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\documentclass[11pt]{article}
%Gummi|065|=)
\usepackage{graphicx}
\usepackage{caption}
\usepackage{xcolor}
\usepackage[vcentering,dvips]{geometry}
\geometry{papersize={6in,9in},total={4.5in,6.8in}}
\title{\textbf{}}
\author{Steak Electronics}
\date{}
\begin{document}
%\maketitle
\tableofcontents
\textcolor{green!60!blue!70}{
\section{60Hz Divider}}
\subsection{Overview}
Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
\begin{center}
\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
\captionof{figure}{60 Hz Logic Divider to 1Hz}
\end{center}
\subsection{Initial Notes: Counting the Hz}
pseudo code goal:
\begin{verbatim}
Using 1Hz signal
Start counting 1MHz every 1Hz
when next cycle is received,
display count
start counting again
\end{verbatim}
That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
4553 x 5
74hct132
1MHz clock (or 6MHz clock), or some variation thereof
jk flip flop
74376 - quad jk flip flop
7476 - jk flip flop
1mhz clk will be main counter,
6 hz or 1 hz will be latch / reset
I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
\subsection{MAX7219 8 digit 7 LED segment Display Driver}
Basic code tested with this was the LedControl arduino library.
\begin{verbatim}
/*
Now we need a LedControl to work with.
***** These pin numbers will probably not work with your hardware *****
pin 12 is connected to the DataIn
pin 11 is connected to the CLK
pin 10 is connected to LOAD
We have only a single MAX72XX.
*/
\end{verbatim}
Some of the lines have to be edited to allow for all digits to be read, and
also to lower intensity of display. I think also a component package (dark
grey clear plastic bag) in front of the leds with intensity 1 is about right.
\subsection{CPLDs}
\begin{verbatim}
http://dangerousprototypes.com/docs/Xilinx_CPLDs:_XC9500_vs_CoolRunner-II
https://www.eevblog.com/forum/fpga/what-are-cplds-do-they-still-play-a-role-how-to-program-them/msg3084581/#msg3084581
https://www.seeedstudio.com/XC9572XL-CPLD-development-board-v1b-p-799.html
\end{verbatim}
Dangerous prototypes has a few
Including the xc2, the xc95, and the coolrunner.
I wanted xc95, so they have one for \$12. not bad.
Looks like bus pirate can program... But I ended up using a Xilinx USB Platform Cable.
\subsubsection{Programming}
Using the XC9500XL series. This chip has some limitations - which are good.
As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
\subsubsection{6KHz clock}
Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
\subsubsection{UART output}
I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
\subsection{Divide by N Counters}
\begin{center}
\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
\end{center}
The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
\subsection{Attiny 6KHz Clock}
A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
to my other project using it. The CPLD works with it, no problem.
\subsection{Parsing of CPLD UART Stream}
Back to the 14 bit stream...
I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
\begin{verbatim}
Example Code Snippet
Let's demonstrate the use of the DDRx,
PORTx and PINx registers from the
following code snippet:
DDRC = 0x0F;
PORTC = 0x0C;
// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
if (PINC == 0b01000000)
PORTC = 0x0B;
else
PORTC = 0x00;
\end{verbatim}
Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}.
\subsection{Max7219 8 digit 7-Segment Display via Uno}
I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
\begin{verbatim}
//https://playground.arduino.cc/Main/LedControl/#Seg7Control
void printNumber(int v) {
int ones;
int tens;
int hundreds;
int thousands;
boolean negative;
if(v < -9999 || v > 9999)
return;
if(v<0) {
negative=true;
v=v*-1;
}
ones=v%10;
v=v/10;
tens=v%10;
v=v/10;
hundreds=v%10;
v=v/10;
thousands=v;
/*if(negative) {
//print character '-' in the leftmost column
lc.setChar(0,4,'-',false);
}
else {
//print a blank in the sign column
lc.setChar(0,4,' ',false);
}*/
//Now print the number digit by digit
lc.setDigit(0,3,(byte)thousands,false);
lc.setDigit(0,2,(byte)hundreds,false);
lc.setDigit(0,1,(byte)tens,false);
lc.setDigit(0,0,(byte)ones,false);
}
\end{verbatim}
Note that I commented out the negative sign on this. My values are always positive.
\includegraphics[scale=0.30]{../pics/DSCN0170.JPG}
\captionof{figure}{Rev A. 60Hz to 4 digits, is updated once per second.}
\subsection{Project Rev A Complete}
With the above complete, I have an initial prototype. The issues with this are the following:
\begin{itemize}
\item Uno reads 14 bit serial stream wrong (timing issues)
\item 7 segment display slightly bright
\item Should add readout of 120 Volts (can get from transformer)
\item Plywood should be replaced with fiberglass
\end{itemize}
It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
\subsection{Related:}
\begin{itemize}
\item https://shepherdingelectrons.blogspot.com/2020/07/uart-transceiver-for-breadboard-computer.html
\end{itemize}
This guide shows a UART created in TTL 74 logic. What's relevant to this project, is how he managed syncing the clocks.
%todo insert picture
\end{document}

+ 221
- 0
60hz_Divider/docs/23.tex~ View File

@ -0,0 +1,221 @@
\documentclass[11pt]{article}
%Gummi|065|=)
\usepackage{graphicx}
\usepackage{caption}
\usepackage{xcolor}
\usepackage[vcentering,dvips]{geometry}
\geometry{papersize={6in,9in},total={4.5in,6.8in}}
\title{\textbf{}}
\author{Steak Electronics}
\date{}
\begin{document}
%\maketitle
\tableofcontents
\textcolor{green!60!blue!70}{
\section{60Hz Divider}}
\subsection{Overview}
Let's count. There is a schematic in Practical Electronics For Beginners 4th edition. I've built that up, and will add some CPLD counter logic, along with a micro to output the SPI to a 7seg counter module.
The goal is relative accuracy. Not absolute. No GPS here. I'm going from 60 to 6,000 cycles.\footnote{Due to limitations of CPLD} This is just meant to be fun.
\begin{center}
\includegraphics[scale=0.15]{../pics/DSCN2964.JPG}
\captionof{figure}{60 Hz Logic Divider to 1Hz}
\end{center}
\subsection{Initial Notes: Counting the Hz}
pseudo code goal:
\begin{verbatim}
Using 1Hz signal
Start counting 1MHz every 1Hz
when next cycle is received,
display count
start counting again
\end{verbatim}
That's all the objective is here. Easy with a micro, but goal is to complete using cmos or 74 logic.
4553 x 5
74hct132
1MHz clock (or 6MHz clock), or some variation thereof
jk flip flop
74376 - quad jk flip flop
7476 - jk flip flop
1mhz clk will be main counter,
6 hz or 1 hz will be latch / reset
I ended up skipping the 74 CMOS, in favor of a CPLD. Practical Electronics also mentions this approach as favored. Even a micro alone could be used. Schematic entry in the CPLD could also be used.
\subsection{MAX7219 8 digit 7 LED segment Display Driver}
Basic code tested with this was the LedControl arduino library.
\begin{verbatim}
/*
Now we need a LedControl to work with.
***** These pin numbers will probably not work with your hardware *****
pin 12 is connected to the DataIn
pin 11 is connected to the CLK
pin 10 is connected to LOAD
We have only a single MAX72XX.
*/
\end{verbatim}
Some of the lines have to be edited to allow for all digits to be read, and
also to lower intensity of display. I think also a component package (dark
grey clear plastic bag) in front of the leds with intensity 1 is about right.
\subsection{CPLDs}
\begin{verbatim}
http://dangerousprototypes.com/docs/Xilinx_CPLDs:_XC9500_vs_CoolRunner-II
https://www.eevblog.com/forum/fpga/what-are-cplds-do-they-still-play-a-role-how-to-program-them/msg3084581/#msg3084581
https://www.seeedstudio.com/XC9572XL-CPLD-development-board-v1b-p-799.html
\end{verbatim}
dangerous prototypes has a few
including the xc2, the xc95, and the coolrunner.
i wanted xc95, so they have one for \$12. not bad.
looks like bus pirate can program... But I ended up using a Xilinx USB Platform Cable.
\subsection{CPLD Programming}
Using the XC9500XL series. This chip has some limitations - which are good.
As you get faster clocks, you need bigger registers to handle parsing the clocks. Bigger registers, use more power. Maybe this is one reason why high clock speeds mean more power.
\subsubsection{6KHz clock}
Due to limitations on the XC9500XL FPGA logic blocks, I ended up limiting the counter registers to 12+1 bits\footnote{Possibly I could use multiple smaller registers in a type of cascade, but let's not bother with that for now. I had 600KHz resolution, until I added the UART out/}, so I have around 6,000 (assuming 60Hz), resolution. With this, I need a 6KHz clock. I could do this with the uno, but let's throw an attiny in there because it's a good tool for this kind of purpose and resolution. It should be able to function as a rough 6KHz timer, easily.
\subsubsection{UART output}
I set the CPLD to use the rising edge of the 6KHz clock and to shift the counter value out... Unsuprisingly, the baud rate is 6000. I found this by using my Open Bench Logic Sniffer\footnote{Phantom 3 in Repairs 2019}. It's fairly quick to configure and get working. Auto detected the UART speed easy.
However, my uart value is 12 - 14 bits, and with uart being an 8 bit protocol, it makes this unconventional. May need to bit bang something. But before that...
\subsection{Divide by N Counters}
\begin{center}
\includegraphics[scale=0.2]{../pics/DSCN2958.JPG}
\captionof{figure}{This divide by 6 counter, appears to not line up with what the TTL Cookbook has for a similar 7490 one.}
\end{center}
The schematics appear to be incorrect for the divide by 6 counter in the Practical Electronics for Beginners book. Having looked at my built up circuit carefully, I see a 20Hz output from the 60Hz. I managed to get my hands on a copy of the TTL Cookbook by Don Lancaster recently, and that details correct divide by 6 and 10 counters (which are different from what's on my proto board), and while I could fix the divide by 6 counter, instead, I'm going to build another divide by 2 counter, and leave the original incorrect one there as a warning (it's also easier to just build a new one).
As it is, I'm getting 2Hz output on the pulse pin... Oops. Practical Untested Electronics for Beginners. Hax. Everything in life is hax. The earlier you realize that, the better you will feel about your own work.\footnote{It's possible they put the error in on purpose. It's really hard to tell...}
\subsection{Attiny 6KHz Clock}
A small victory here: I setup an Attiny10 with an external oscillator (programmable CMOS, not Quartz) of 1.536MHz. I then set prescaler at 256 to get
6000. Set micro fuse to enable CKOUT pin, and now I have a 6KHz clock from the 20 cent micro plus. Neat usage of the attiny10 here, thanks
to my other project using it. The CPLD works with it, no problem.
\subsection{Parsing of CPLD UART Stream}
Back to the 14 bit stream...
I have the UART stream feeding into the Atmega328/Uno. For the code, I was unsure how to handle it at first, but then I realized a simple shift in would fit.
\textbf{Situation:} I have a serial UART stream at 6000 baud from the CPLD. However, it's not exactly UART. In fact, it has values of 6000, which are over 8 bit. So I have a 14 bit serial stream. There is no stop bit after the 8 bits, and no two 8 bit bytes. So hardware serial will not work. \footnote{I didn't want to deal with coding the UART into the CPLD. There are also size limitations.}
\textbf{Solution:} I have a serial 14 bit stream at 6000 baud. The answer is to tie the 6000 Hz CLK to a pin on the Uno, and implement a shift in, so that every clock up, the value is read on the Serial / 14 bit pin. I do have a start bit, and I am not outputting all the time, so this will be one 14 bit value every second.
\textbf{Problems:} The Uno's digitalRead timing is not 100\% As a result, some values are being read incorrectly. 5996 shows up as 5048 or similar. I need to go back and access the Input direct via register reads to speed things up. A Pin register access similar to:
\begin{verbatim}
Example Code Snippet
Let's demonstrate the use of the DDRx,
PORTx and PINx registers from the
following code snippet:
DDRC = 0x0F;
PORTC = 0x0C;
// lets assume a 4V supply comes to PORTC.6 and Vcc = 5V
if (PINC == 0b01000000)
PORTC = 0x0B;
else
PORTC = 0x00;
\end{verbatim}
Reference: http://maxembedded.com/2011/06/port-operations-in-avr/
may fix these issues. In the meantime, because the errors are consistent, I setup some LUTs\footnote{Lookup tables, i.e. hard coded fixes. e.g. 5048 now converts to 5996.}.
\subsection{Max7219 8 digit 7-Segment Display via Uno}
I didn't have any trouble getting the 7 segment to display with the Uno and the Max7219. Note that I avoided outputting the values via the CPLD. The Uno is just quicker to code this output. I used the LedControl library. I had to adopt a quick function to break down the values. The Max7219 does not take in variables, so instead, you feed it single digits. Therefore I needed to extract a single digit from the tens, hundreds, and thousands. See below:
\begin{verbatim}
//https://playground.arduino.cc/Main/LedControl/#Seg7Control
void printNumber(int v) {
int ones;
int tens;
int hundreds;
int thousands;
boolean negative;
if(v < -9999 || v > 9999)
return;
if(v<0) {
negative=true;
v=v*-1;
}
ones=v%10;
v=v/10;
tens=v%10;
v=v/10;
hundreds=v%10;
v=v/10;
thousands=v;
/*if(negative) {
//print character '-' in the leftmost column
lc.setChar(0,4,'-',false);
}
else {
//print a blank in the sign column
lc.setChar(0,4,' ',false);
}*/
//Now print the number digit by digit
lc.setDigit(0,3,(byte)thousands,false);
lc.setDigit(0,2,(byte)hundreds,false);
lc.setDigit(0,1,(byte)tens,false);
lc.setDigit(0,0,(byte)ones,false);
}
\end{verbatim}
Note that I commented out the negative sign on this. My values are always positive.
\includegraphics[scale=0.30]{../pics/DSCN0170.JPG}
\captionof{figure}{Rev A. 60Hz to 4 digits, is updated once per second.}
\subsection{Project Rev A Complete}
With the above complete, I have an initial prototype. The issues with this are the following:
\begin{itemize}
\item Uno reads 14 bit serial stream wrong (timing issues)
\item 7 segment display slightly bright
\item Should add readout of 120 Volts (can get from transformer)
\item Plywood should be replaced with fiberglass
\end{itemize}
It turns out that 4 digits on the display is the minimum for a project like this to be viable. 3 digits wouldn't be enough resolution, and 5 digits is not necessary (although nice). The values differ here from about 5996 to 6003 cycles per second.
Other than that, it is working, and will be setup and watched for a bit to enjoy the readout.
\subsection{Related:}
\begin{itemize}
\item https://shepherdingelectrons.blogspot.com/2020/07/uart-transceiver-for-breadboard-computer.html
\end{itemize}
This guide shows a UART created in TTL 74 logic. What's relevant to this project, is how he managed syncing the clocks.
%todo insert picture
\end{document}

+ 14
- 0
60hz_Divider/docs/23.toc View File

@ -0,0 +1,14 @@
\contentsline {section}{\numberline {1}60Hz Divider}{1}%
\contentsline {subsection}{\numberline {1.1}Overview}{1}%
\contentsline {subsection}{\numberline {1.2}Initial Notes: Counting the Hz}{2}%
\contentsline {subsection}{\numberline {1.3}MAX7219 8 digit 7 LED segment Display Driver}{2}%
\contentsline {subsection}{\numberline {1.4}CPLDs}{3}%
\contentsline {subsubsection}{\numberline {1.4.1}Programming}{3}%
\contentsline {subsubsection}{\numberline {1.4.2}6KHz clock}{4}%
\contentsline {subsubsection}{\numberline {1.4.3}UART output}{4}%
\contentsline {subsection}{\numberline {1.5}Divide by N Counters}{4}%
\contentsline {subsection}{\numberline {1.6}Attiny 6KHz Clock}{5}%
\contentsline {subsection}{\numberline {1.7}Parsing of CPLD UART Stream}{5}%
\contentsline {subsection}{\numberline {1.8}Max7219 8 digit 7-Segment Display via Uno}{7}%
\contentsline {subsection}{\numberline {1.9}Project Rev A Complete}{8}%
\contentsline {subsection}{\numberline {1.10}Related:}{9}%

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<h1 id="firstHeading" class="firstHeading">CPLD: Complex programmable logic devices</h1>
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<tr>
<th style="text-align: center; color: #fff; border: 1px solid #1E7B8E; background-color:#1E7B8E; font-size: 11px;" colspan="2">Project Summary
</th></tr>
<tr>
<td colspan="2">
</td></tr>
<tr>
<th> Name:
</th><td> CPLD: Complex programmable logic devices
</td></tr>
<tr>
<th> Buy it:
</th><td> <a href="http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html?cPath=174" class="external text" rel="nofollow">Get one for $15 at Seeed Studio</a>
</td></tr>
<tr>
<th> Price:
</th><td> $15
</td></tr>
<tr>
<th> Status:
</th><td> <a href="/docs/Project_status#Development_status" title="Project status">Mature</a>
</td></tr>
<tr>
<th> Manufacturing:
</th><td> <a href="/docs/Project_status#Manufacturing" title="Project status">Shipping</a>
</td></tr>
<tr>
<th> Forum:
</th><td> <a href="http://dangerousprototypes.com/forum/viewforum.php?f=51" class="external text" rel="nofollow">CPLD: Complex programmable logic devices Forum</a>
</td></tr></table><a href="/docs/File:Xc9572-cpld-breakoutvib.jpg" class="image"><img alt="Xc9572-cpld-breakoutvib.jpg" src="/docs/images/6/6c/Xc9572-cpld-breakoutvib.jpg" width="490" height="277" /></a>
<p>Ever get stuck choosing the right logic chip combination or voltage level translator? Give up the hunt and create your own custom logic chip. CPLDs can give you the logic you need, with the pinout you want, while saving board space and board revisions.
</p><p>Development boards from Dangerous Prototypes will help you build your first custom logic chip using simple schematic entry, Verilog, or VHDL.
</p>
<ul><li>XC9572XL or XC2C64A CPLDs
</li><li>On-board power supply for core and pins
</li><li>Selectable 3.3volt or external supply for pins (1.8volt to 3.3volt)
</li><li>LEDs for output, push button for input
</li><li>Easy to program with the Bus Pirate
</li><li>Open source (CC-BY-SA)
</li></ul>
<p><b><a href="http://www.seeedstudio.com/depot/xc2c64a-coolrunnerii-cpld-development-board-p-800.html" class="external text" rel="nofollow">CoolRunner-II</a> and <a href="http://www.seeedstudio.com/depot/xc9572xl-cpld-development-board-p-799.html" class="external text" rel="nofollow">XC9572XL</a> versions available for $15.</b>
</p>
<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
<ul>
<li class="toclevel-1 tocsection-1"><a href="#Downloads"><span class="tocnumber">1</span> <span class="toctext">Downloads</span></a></li>
<li class="toclevel-1 tocsection-2"><a href="#Hardware"><span class="tocnumber">2</span> <span class="toctext">Hardware</span></a>
<ul>
<li class="toclevel-2 tocsection-3"><a href="#XC9500XL"><span class="tocnumber">2.1</span> <span class="toctext">XC9500XL</span></a></li>
<li class="toclevel-2 tocsection-4"><a href="#CoolRunnerII"><span class="tocnumber">2.2</span> <span class="toctext">CoolRunnerII</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-5"><a href="#CPLD_development_tutorials"><span class="tocnumber">3</span> <span class="toctext">CPLD development tutorials</span></a>
<ul>
<li class="toclevel-2 tocsection-6"><a href="#Schematic_entry"><span class="tocnumber">3.1</span> <span class="toctext">Schematic entry</span></a></li>
<li class="toclevel-2 tocsection-7"><a href="#Verilog"><span class="tocnumber">3.2</span> <span class="toctext">Verilog</span></a></li>
<li class="toclevel-2 tocsection-8"><a href="#VHDL"><span class="tocnumber">3.3</span> <span class="toctext">VHDL</span></a></li>
<li class="toclevel-2 tocsection-9"><a href="#Plunify"><span class="tocnumber">3.4</span> <span class="toctext">Plunify</span></a></li>
<li class="toclevel-2 tocsection-10"><a href="#ISE_Webpack"><span class="tocnumber">3.5</span> <span class="toctext">ISE Webpack</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-11"><a href="#Example_devices"><span class="tocnumber">4</span> <span class="toctext">Example devices</span></a>
<ul>
<li class="toclevel-2 tocsection-12"><a href="#Schematic"><span class="tocnumber">4.1</span> <span class="toctext">Schematic</span></a></li>
<li class="toclevel-2 tocsection-13"><a href="#VHDL_2"><span class="tocnumber">4.2</span> <span class="toctext">VHDL</span></a></li>
<li class="toclevel-2 tocsection-14"><a href="#Verilog_2"><span class="tocnumber">4.3</span> <span class="toctext">Verilog</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-15"><a href="#Programming"><span class="tocnumber">5</span> <span class="toctext">Programming</span></a>
<ul>
<li class="toclevel-2 tocsection-16"><a href="#Additional_methods"><span class="tocnumber">5.1</span> <span class="toctext">Additional methods</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-17"><a href="#Links"><span class="tocnumber">6</span> <span class="toctext">Links</span></a>
<ul>
<li class="toclevel-2 tocsection-18"><a href="#Verilog_3"><span class="tocnumber">6.1</span> <span class="toctext">Verilog</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-19"><a href="#Resources"><span class="tocnumber">7</span> <span class="toctext">Resources</span></a></li>
<li class="toclevel-1 tocsection-20"><a href="#License"><span class="tocnumber">8</span> <span class="toctext">License</span></a></li>
</ul>
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<h2> <span class="mw-headline" id="Downloads">Downloads</span></h2>
<ul><li><a href="https://github.com/DangerousPrototypes/Downloads/blob/master/CPLD.Breakout.Package.v1.0.zip" class="external text" rel="nofollow">Download CPLD Breakout Package</a>
</li><li><a href="https://github.com/DangerousPrototypes/CPLD_Breakout" class="external text" rel="nofollow">Browse the project's GitHub</a>
</li></ul>
<h2> <span class="mw-headline" id="Hardware">Hardware</span></h2>
<ul><li><a href="/docs/Xilinx_CPLDs:_XC9500_vs_CoolRunner-II" title="Xilinx CPLDs: XC9500 vs CoolRunner-II">Xilinx CPLDs: XC9500 vs CoolRunner-II</a>
</li></ul>
<h3> <span class="mw-headline" id="XC9500XL">XC9500XL</span></h3>
<p><a href="/docs/File:Xc9572-cpld-breakoutvib.jpg" class="image"><img alt="Xc9572-cpld-breakoutvib.jpg" src="/docs/images/thumb/6/6c/Xc9572-cpld-breakoutvib.jpg/150px-Xc9572-cpld-breakoutvib.jpg" width="150" height="85" /></a>
</p><p>The Xilinx XC9500XL family has some of the cheapest and readily available CPLDs out there. Inputs are 5volt tolerant and they can be run from a single 3.3volt supply.
</p>
<ul><li><a href="/docs/XC9500XL_CPLD_breakout_board" title="XC9500XL CPLD breakout board">XC9500XL CPLD development board</a> hardware design
</li><li><a href="/docs/XC9572XL_CPLD_dev-board_introduction" title="XC9572XL CPLD dev-board introduction">XC9572XL CPLD dev-board introduction</a>
</li><li><a href="/docs/Xilinx_XC9500XL_CPLD_quick_start" title="Xilinx XC9500XL CPLD quick start">XC9500XL CPLD quick start</a>
</li><li><a href="/docs/XC9572XL_dev-board_v1_errors" title="XC9572XL dev-board v1 errors">XC9572XL dev-board v1 errors</a>
</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds054.pdf" class="external text" rel="nofollow">XC9500XL family manual</a>
</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds057.pdf" class="external text" rel="nofollow">XC9572XL device datasheet</a>
</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds058.pdf" class="external text" rel="nofollow">XC9536XL device datasheet</a> (smaller version of XC9572XL)
</li></ul>
<h3> <span class="mw-headline" id="CoolRunnerII">CoolRunnerII</span></h3>
<p><a href="/docs/File:Xc2c64a_cpld_breakout-vib.jpg" class="image"><img alt="Xc2c64a cpld breakout-vib.jpg" src="/docs/images/thumb/7/70/Xc2c64a_cpld_breakout-vib.jpg/150px-Xc2c64a_cpld_breakout-vib.jpg" width="150" height="84" /></a>
</p><p>The CoolRunner-II family is newer than the XC9500XL, and has a few extra features like multiple IO voltage banks for voltage translation, internal pull-up resistors and pin keepers and a clock divider. Requires a 1.8volt core supply and a 1.2-3.3volt IO pin supply.
</p>
<ul><li><a href="/docs/CoolRunner-II_CPLD_breakout_board" title="CoolRunner-II CPLD breakout board">CoolRunner-II CPLD development board</a> hardware design
</li><li><a href="/docs/XC2C64A_CPLD_dev-board_introduction" title="XC2C64A CPLD dev-board introduction">XC2C64A CPLD dev-board introduction</a>
</li><li><a href="/docs/Xilinx_CoolRunner-II_CPLD_quick_start" title="Xilinx CoolRunner-II CPLD quick start">CoolRunner-II CPLD quick start</a>
</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf" class="external text" rel="nofollow">CoolRunner-II family manual</a>
</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds311.pdf" class="external text" rel="nofollow">XC2C64A device datasheet</a>
</li><li><a href="http://www.xilinx.com/support/documentation/data_sheets/ds310.pdf" class="external text" rel="nofollow">XC2C32A device datasheet</a> (smaller version of XC2C64A used on Bus Blaster v2)
</li></ul>
<h2> <span class="mw-headline" id="CPLD_development_tutorials">CPLD development tutorials</span></h2>
<p>This tutorial shows how to use simple schematics to design the logic in a Xilinx CoolRunner-II or XC9500 CPLD.
</p>
<ul><li><a href="http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html" class="external text" rel="nofollow">Free Xilinx ISE Webpack download</a>
</li></ul>
<p>Tutorial files:
</p>
<ul><li>See <a href="https://github.com/DangerousPrototypes/Downloads/blob/master/CPLDdev.package.v1.1.zip" class="external text" rel="nofollow">CPLDdev.package.v1.1.zip</a>
</li></ul>
<p>The Bus Pirate XSVF player and a .bat file are included with every example. Modify the COM post and click to load.
</p>
<h3> <span class="mw-headline" id="Schematic_entry">Schematic entry</span></h3>
<ul><li><a href="/docs/CPLD_intro_1:_Light_a_LED" title="CPLD intro 1: Light a LED">CPLD intro 1: Light a LED</a>
</li><li><a href="/docs/CPLD_intro_2:_Toggle_a_LED_with_a_button" title="CPLD intro 2: Toggle a LED with a button">CPLD intro 2: Toggle a LED with a button</a>
</li><li><a href="/docs/CPLD_intro_3:_Inverse_LED_toggle" title="CPLD intro 3: Inverse LED toggle">CPLD intro 3: Inverse LED toggle</a>
</li></ul>
<h3> <span class="mw-headline" id="Verilog">Verilog</span></h3>
<ul><li><a href="/docs/CPLD_Verilog_intro_1:_Light_a_LED" title="CPLD Verilog intro 1: Light a LED">CPLD Verilog intro 1: Light a LED</a>
</li><li><a href="/docs/CPLD_Verilog_intro_2:_Toggle_a_LED_with_a_button" title="CPLD Verilog intro 2: Toggle a LED with a button">CPLD Verilog intro 2: Toggle a LED with a button</a>
</li><li><a href="/docs/CPLD_Verilog_intro_3:_Inverse_LED_toggle" title="CPLD Verilog intro 3: Inverse LED toggle">CPLD Verilog intro 3: Inverse LED toggle</a>
</li></ul>
<h3> <span class="mw-headline" id="VHDL">VHDL</span></h3>
<ul><li><a href="/docs/CPLD_VHDL_intro_1:_Light_a_LED" title="CPLD VHDL intro 1: Light a LED">CPLD VHDL intro 1: Light a LED</a>
</li><li><a href="/docs/CPLD_VHDL_intro_2:_Toggle_a_LED_with_a_button" title="CPLD VHDL intro 2: Toggle a LED with a button">CPLD VHDL intro 2: Toggle a LED with a button</a>
</li><li><a href="/docs/CPLD_VHDL_intro_3:_Inverse_LED_toggle" title="CPLD VHDL intro 3: Inverse LED toggle">CPLD VHDL intro 3: Inverse LED toggle</a>
</li><li><a href="/docs/CPLD_intro_4:_replacing_simple_logic_vhdl" title="CPLD intro 4: replacing simple logic vhdl">CPLD VHDL intro 4: Replacing simple logic</a>
</li></ul>
<h3> <span class="mw-headline" id="Plunify">Plunify</span></h3>
<p><a href="http://www.plunify.com" class="external text" rel="nofollow">Plunify</a> is a cloud-based compiler for <s>Xilinx</s> and Altera chips. <s>The CPLD examples are already loaded, all you have to do is sign up for a free account and copy the tutorial from the <i>add IP</i> tab.</s> Unfortunately it no longer supports Xilinx chips.
</p>
<ul><li><a href="http://www.youtube.com/watch?v=WWFyVMZUMRE" class="external text" rel="nofollow">How-to video: use Plunify with the CPLD examples</a>
</li><li><a href="/docs/Plunify_online_compiler_overview" title="Plunify online compiler overview">Plunify online compiler overview</a>
</li></ul>
<h3> <span class="mw-headline" id="ISE_Webpack">ISE Webpack</span></h3>
<ul><li><a href="/docs/Export_(X)SVF_from_Xilinx_ISE_Webpack" title="Export (X)SVF from Xilinx ISE Webpack">Export (X)SVF from Xilinx ISE Webpack</a>
</li><li><a href="/docs/CPLD:_simulate_designs" title="CPLD: simulate designs">CPLD: simulate designs</a>
</li><li><a href="/docs/Enable_CoolRunner-II_CPLD_pull-up_resistors" title="Enable CoolRunner-II CPLD pull-up resistors">Enable CoolRunner-II CPLD pull-up resistors</a>
</li></ul>
<h2> <span class="mw-headline" id="Example_devices">Example devices</span></h2>
<ul><li><a href="https://github.com/DangerousPrototypes/Downloads/blob/master/CPLDdev.package.v1.1.zip" class="external text" rel="nofollow">CPLDdev.package.v1.1.zip</a>
</li><li><a href="https://github.com/DangerousPrototypes/CPLD_Breakout/tree/master/package/Device_examples" class="external text" rel="nofollow">Latest in SVN</a>
</li></ul>
<h3> <span class="mw-headline" id="Schematic">Schematic</span></h3>
<ul><li><a href="/docs/CPLD_example:_Dual_74xx595s" title="CPLD example: Dual 74xx595s">CPLD example: Dual 74xx595s</a>
</li><li><a href="/docs/CPLD_example:_Dual_latch" title="CPLD example: Dual latch">CPLD example: Dual latch</a>
</li><li><a href="/docs/CPLD_example:_FIFO" title="CPLD example: FIFO">CPLD example: FIFO</a>
</li><li><a href="/docs/CPLD_example:_Motor_Phase_Interlock" title="CPLD example: Motor Phase Interlock">CPLD example: Motor Phase Interlock</a>
</li><li><a href="/docs/CPLD_example:_Priority_Decoder" title="CPLD example: Priority Decoder">CPLD example: Priority Decoder</a>
</li><li><a href="/docs/CPLD_example:_PWM_Generator" title="CPLD example: PWM Generator">CPLD example: PWM Generator</a>
</li><li><a href="/docs/CPLD_example:_Addressable_Latch" title="CPLD example: Addressable Latch">CPLD example: Addressable Latch</a>
</li></ul>
<h3> <span class="mw-headline" id="VHDL_2">VHDL</span></h3>
<ul><li>Our <a href="/docs/7400_series_library_in_VHDL" title="7400 series library in VHDL">7400 series library in VHDL</a>
</li><li><a href="http://opencores.org/project,mcpu" class="external text" rel="nofollow">32 macrocell CPU</a> at OpenCores.org
</li><li><a href="/docs/CPLD_ring_oscillator" title="CPLD ring oscillator">CPLD ring oscillator</a> a clock source without a crystal
</li></ul>
<h3> <span class="mw-headline" id="Verilog_2">Verilog</span></h3>
<ul><li><a href="/docs/Lulu:_Yet_another_logic_analyzer" title="Lulu: Yet another logic analyzer">Logic analyzer example in 72 macrocells</a>
</li></ul>
<h2> <span class="mw-headline" id="Programming">Programming</span></h2>
<ul><li><a href="/docs/Bus_Pirate_JTAG_XSVF_player" title="Bus Pirate JTAG XSVF player">CPLD programming with Bus Pirate, XSVF loader, and XSVF files</a>
</li><li><a href="/docs/CPLD_programming_with_Bus_Blaster,_urJTAG,_and_SVF_files" title="CPLD programming with Bus Blaster, urJTAG, and SVF files">CPLD programming with Bus Blaster, urJTAG, and SVF files</a> (currently CoolRunner-II only)
</li><li><a href="/docs/JTAG_SVF_to_XSVF_file_converter" title="JTAG SVF to XSVF file converter">JTAG SVF to XSVF file converter</a>
</li></ul>
<h3> <span class="mw-headline" id="Additional_methods">Additional methods</span></h3>
<ul><li><a href="http://www.xilinx.com/itp/3_1i/pdf/docs/jtg/jtg.pdf" class="external text" rel="nofollow">Parallel cables with IMPACT</a>
</li><li><a href="http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf" class="external text" rel="nofollow">XSVF player for any microcontroller</a> (used in Bus Pirate XSVF player)
</li><li><a href="http://www.clifford.at/libxsvf/" class="external text" rel="nofollow">lib(X)SVF</a>
</li><li><a href="http://rmdir.de/~michael/xilinx/" class="external text" rel="nofollow">FT2232 programmers and IMPACT with alternate driver</a>
</li></ul>
<h2> <span class="mw-headline" id="Links">Links</span></h2>
<h3> <span class="mw-headline" id="Verilog_3">Verilog</span></h3>
<ul><li><a href="http://www.asic-world.com/verilog/synthesis.html" class="external text" rel="nofollow">Synthesis tutorial</a> (a favorite tutorial)
</li><li><a href="http://www.asic-world.com/tidbits/index.html" class="external text" rel="nofollow">Verilog concepts</a> (wire, reg, blocking, etc)
</li></ul>
<h2> <span class="mw-headline" id="Resources">Resources</span></h2>
<ul><li><a href="/docs/Xilinx_CPLD_breakout_development_scraps" title="Xilinx CPLD breakout development scraps">Xilinx CPLD breakout development scraps</a>
</li><li><a href="/docs/CPLD_development_board_manufacturing_resources" title="CPLD development board manufacturing resources">CPLD development board manufacturing resources</a>
</li></ul>
<h2> <span class="mw-headline" id="License">License</span></h2>
<ul><li>Hardware: CC-BY-SA
</li><li>CPLD demos projects: CC-0
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